Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2697396	1			T1	5		T3	1		T4	1
all_pins[1]	2697396	1			T1	5		T3	1		T4	1
all_pins[2]	2697396	1			T1	5		T3	1		T4	1
all_pins[3]	2697396	1			T1	5		T3	1		T4	1
all_pins[4]	2697396	1			T1	5		T3	1		T4	1
all_pins[5]	2697396	1			T1	5		T3	1		T4	1
all_pins[6]	2697396	1			T1	5		T3	1		T4	1
all_pins[7]	2697396	1			T1	5		T3	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21406348	1			T1	40		T3	8		T4	8
values[0x1]	172820	1			T20	18		T38	248		T64	7
transitions[0x0=>0x1]	170895	1			T20	10		T38	191		T64	4
transitions[0x1=>0x0]	170912	1			T20	10		T38	192		T64	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2696724	1			T1	5		T3	1		T4	1
all_pins[0]	values[0x1]	672	1			T20	1		T38	174		T63	2
all_pins[0]	transitions[0x0=>0x1]	446	1			T20	1		T38	138		T63	1
all_pins[0]	transitions[0x1=>0x0]	293	1			T20	3		T38	2		T160	3
all_pins[1]	values[0x0]	2696877	1			T1	5		T3	1		T4	1
all_pins[1]	values[0x1]	519	1			T20	3		T38	38		T63	1
all_pins[1]	transitions[0x0=>0x1]	369	1			T20	1		T38	26		T63	1
all_pins[1]	transitions[0x1=>0x0]	153	1			T38	3		T34	1		T160	2
all_pins[2]	values[0x0]	2697093	1			T1	5		T3	1		T4	1
all_pins[2]	values[0x1]	303	1			T20	2		T38	15		T34	37
all_pins[2]	transitions[0x0=>0x1]	249	1			T20	1		T38	13		T34	37
all_pins[2]	transitions[0x1=>0x0]	156	1			T20	2		T38	4		T64	2
all_pins[3]	values[0x0]	2697186	1			T1	5		T3	1		T4	1
all_pins[3]	values[0x1]	210	1			T20	3		T38	6		T64	2
all_pins[3]	transitions[0x0=>0x1]	155	1			T20	2		T38	4		T34	1
all_pins[3]	transitions[0x1=>0x0]	145	1			T64	1		T34	2		T160	5
all_pins[4]	values[0x0]	2697196	1			T1	5		T3	1		T4	1
all_pins[4]	values[0x1]	200	1			T20	1		T38	2		T64	3
all_pins[4]	transitions[0x0=>0x1]	161	1			T38	1		T64	2		T160	4
all_pins[4]	transitions[0x1=>0x0]	1557	1			T38	1		T63	1		T34	488
all_pins[5]	values[0x0]	2695800	1			T1	5		T3	1		T4	1
all_pins[5]	values[0x1]	1596	1			T20	1		T38	2		T64	1
all_pins[5]	transitions[0x0=>0x1]	320	1			T38	2		T64	1		T63	1
all_pins[5]	transitions[0x1=>0x0]	167819	1			T20	4		T38	3		T63	1
all_pins[6]	values[0x0]	2528301	1			T1	5		T3	1		T4	1
all_pins[6]	values[0x1]	169095	1			T20	5		T38	3		T63	1
all_pins[6]	transitions[0x0=>0x1]	169041	1			T20	3		T38	2		T34	85930
all_pins[6]	transitions[0x1=>0x0]	171	1			T38	7		T64	1		T63	2
all_pins[7]	values[0x0]	2697171	1			T1	5		T3	1		T4	1
all_pins[7]	values[0x1]	225	1			T20	2		T38	8		T64	1
all_pins[7]	transitions[0x0=>0x1]	154	1			T20	2		T38	5		T64	1
all_pins[7]	transitions[0x1=>0x0]	618	1			T20	1		T38	172		T34	221