Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3496	1			T8	23		T9	20		T11	20
values[1]	2922	1			T9	73		T11	33		T106	16
values[2]	3134	1			T8	20		T9	20		T11	26
values[3]	3289	1			T4	12		T8	45		T9	50
values[4]	3257	1			T3	4		T8	20		T9	68
values[5]	3463	1			T8	21		T37	4		T29	27
values[6]	2995	1			T8	45		T9	77		T11	25
values[7]	3722	1			T8	20		T9	40		T11	164

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3000	1			T3	4		T4	12		T8	20
values[1]	3347	1			T8	45		T9	70		T11	26
values[2]	3366	1			T9	20		T12	10		T14	14
values[3]	3863	1			T9	97		T11	20		T29	67
values[4]	2839	1			T9	48		T11	112		T162	2
values[5]	2702	1			T11	110		T29	42		T85	4
values[6]	3248	1			T8	40		T9	41		T11	20
values[7]	3913	1			T8	89		T9	72		T11	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25823

1

T3

4

T4

12

T8

192

auto[1]

455

1

T8

2

T9

4

T11

16

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[2]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	533	1			T163	4		T164	110		T165	52
auto[0]	values[0]	values[1]	394	1			T31	64		T24	19		T166	6
auto[0]	values[0]	values[2]	299	1			T9	20		T105	10		T27	64
auto[0]	values[0]	values[3]	408	1			T29	40		T35	57		T36	45
auto[0]	values[0]	values[4]	352	1			T11	17		T33	18		T167	20
auto[0]	values[0]	values[5]	332	1			T29	42		T32	27		T168	12
auto[0]	values[0]	values[6]	449	1			T34	28		T36	41		T169	18
auto[0]	values[0]	values[7]	664	1			T8	23		T21	14		T34	20
auto[0]	values[1]	values[0]	362	1			T33	19		T170	4		T35	18
auto[0]	values[1]	values[1]	133	1			T171	6		T172	20		T173	2
auto[0]	values[1]	values[2]	244	1			T51	20		T174	10		T175	20
auto[0]	values[1]	values[3]	679	1			T164	97		T176	85		T177	19
auto[0]	values[1]	values[4]	254	1			T11	31		T162	2		T36	20
auto[0]	values[1]	values[5]	277	1			T178	44		T172	20		T179	4
auto[0]	values[1]	values[6]	462	1			T9	40		T106	16		T180	45
auto[0]	values[1]	values[7]	455	1			T9	31		T181	6		T33	45
auto[0]	values[2]	values[0]	286	1			T8	20		T35	20		T182	15
auto[0]	values[2]	values[1]	405	1			T11	26		T51	45		T178	71
auto[0]	values[2]	values[2]	432	1			T14	14		T34	20		T35	29
auto[0]	values[2]	values[3]	496	1			T9	20		T34	21		T51	20
auto[0]	values[2]	values[4]	340	1			T178	19		T183	20		T184	8
auto[0]	values[2]	values[5]	360	1			T32	18		T34	20		T185	2
auto[0]	values[2]	values[6]	456	1			T123	4		T33	19		T186	12
auto[0]	values[2]	values[7]	319	1			T187	16		T188	14		T178	48
auto[0]	values[3]	values[0]	349	1			T4	12		T26	21		T189	16
auto[0]	values[3]	values[1]	588	1			T8	25		T9	50		T34	49
auto[0]	values[3]	values[2]	444	1			T32	20		T51	20		T126	20
auto[0]	values[3]	values[3]	531	1			T11	19		T80	14		T33	19
auto[0]	values[3]	values[4]	310	1			T190	4		T180	20		T44	20
auto[0]	values[3]	values[5]	166	1			T34	21		T178	17		T165	33
auto[0]	values[3]	values[6]	478	1			T8	20		T35	101		T164	43
auto[0]	values[3]	values[7]	364	1			T24	20		T191	20		T192	29
auto[0]	values[4]	values[0]	421	1			T3	4		T32	37		T27	20
auto[0]	values[4]	values[1]	365	1			T29	19		T32	20		T33	20
auto[0]	values[4]	values[2]	461	1			T193	6		T194	4		T33	20
auto[0]	values[4]	values[3]	444	1			T195	6		T196	39		T197	20
auto[0]	values[4]	values[4]	397	1			T9	47		T34	20		T198	10
auto[0]	values[4]	values[5]	255	1			T27	62		T49	14		T199	4
auto[0]	values[4]	values[6]	350	1			T11	19		T33	20		T51	41
auto[0]	values[4]	values[7]	495	1			T8	20		T9	20		T29	16
auto[0]	values[5]	values[0]	207	1			T33	20		T24	23		T126	32
auto[0]	values[5]	values[1]	635	1			T37	4		T121	4		T27	36
auto[0]	values[5]	values[2]	446	1			T82	20		T180	115		T191	20
auto[0]	values[5]	values[3]	321	1			T29	26		T27	20		T200	14
auto[0]	values[5]	values[4]	423	1			T201	20		T202	90		T203	10
auto[0]	values[5]	values[5]	393	1			T50	34		T24	18		T126	21
auto[0]	values[5]	values[6]	305	1			T32	20		T167	22		T172	55
auto[0]	values[5]	values[7]	689	1			T8	20		T32	87		T91	6
auto[0]	values[6]	values[0]	295	1			T48	4		T204	4		T205	2
auto[0]	values[6]	values[1]	217	1			T206	20		T177	19		T207	6
auto[0]	values[6]	values[2]	602	1			T12	8		T32	20		T208	18
auto[0]	values[6]	values[3]	415	1			T9	76		T24	23		T209	4
auto[0]	values[6]	values[4]	239	1			T210	10		T34	20		T191	20
auto[0]	values[6]	values[5]	395	1			T11	24		T85	4		T34	21
auto[0]	values[6]	values[6]	380	1			T8	19		T34	19		T24	24
auto[0]	values[6]	values[7]	393	1			T8	25		T29	42		T92	18
auto[0]	values[7]	values[0]	485	1			T27	73		T33	51		T178	35
auto[0]	values[7]	values[1]	565	1			T8	20		T9	20		T27	204
auto[0]	values[7]	values[2]	394	1			T32	20		T27	20		T211	21
auto[0]	values[7]	values[3]	507	1			T212	8		T34	19		T164	219
auto[0]	values[7]	values[4]	459	1			T11	58		T24	40		T167	22
auto[0]	values[7]	values[5]	462	1			T11	79		T213	6		T55	33
auto[0]	values[7]	values[6]	309	1			T214	63		T51	20		T215	2
auto[0]	values[7]	values[7]	478	1			T9	20		T11	19		T32	59
auto[1]	values[0]	values[0]	7	1			T164	1		T165	2		T216	1
auto[1]	values[0]	values[1]	6	1			T24	1		T217	1		T197	2
auto[1]	values[0]	values[3]	8	1			T24	1		T206	2		T165	3
auto[1]	values[0]	values[4]	23	1			T11	3		T33	2		T152	3
auto[1]	values[0]	values[5]	5	1			T32	1		T177	1		T218	2
auto[1]	values[0]	values[6]	9	1			T36	1		T219	4		T220	1
auto[1]	values[0]	values[7]	7	1			T221	2		T222	2		T223	1
auto[1]	values[1]	values[0]	12	1			T33	1		T35	2		T36	2
auto[1]	values[1]	values[1]	1	1			T152	1		-	-		-	-
auto[1]	values[1]	values[2]	5	1			T224	1		T225	4		-	-
auto[1]	values[1]	values[3]	11	1			T164	3		T177	1		T226	1
auto[1]	values[1]	values[4]	4	1			T11	2		T224	1		T223	1
auto[1]	values[1]	values[5]	9	1			T178	3		T224	2		T227	2
auto[1]	values[1]	values[6]	7	1			T9	1		T178	4		T228	1
auto[1]	values[1]	values[7]	7	1			T9	1		T33	1		T172	2
auto[1]	values[2]	values[0]	8	1			T182	5		T229	1		T224	1
auto[1]	values[2]	values[1]	1	1			T178	1		-	-		-	-
auto[1]	values[2]	values[2]	1	1			T192	1		-	-		-	-
auto[1]	values[2]	values[3]	3	1			T34	1		T172	1		T230	1
auto[1]	values[2]	values[4]	5	1			T178	1		T231	2		T227	2
auto[1]	values[2]	values[5]	3	1			T32	2		T232	1		-	-
auto[1]	values[2]	values[6]	9	1			T33	1		T191	2		T196	1
auto[1]	values[2]	values[7]	10	1			T192	1		T197	2		T25	1
auto[1]	values[3]	values[0]	10	1			T189	2		T233	3		T234	2
auto[1]	values[3]	values[1]	11	1			T34	2		T180	1		T182	1
auto[1]	values[3]	values[2]	8	1			T51	2		T25	1		T45	1
auto[1]	values[3]	values[3]	8	1			T11	1		T33	1		T235	1
auto[1]	values[3]	values[4]	7	1			T196	2		T236	1		T237	3
auto[1]	values[3]	values[5]	6	1			T178	3		T165	1		T238	2
auto[1]	values[3]	values[6]	5	1			T35	1		T225	4		-	-
auto[1]	values[3]	values[7]	4	1			T24	1		T234	1		T131	2
auto[1]	values[4]	values[0]	5	1			T32	2		T44	2		T196	1
auto[1]	values[4]	values[1]	12	1			T29	1		T197	2		T221	1
auto[1]	values[4]	values[2]	8	1			T126	1		T239	2		T236	1
auto[1]	values[4]	values[3]	8	1			T196	2		T240	2		T25	1
auto[1]	values[4]	values[4]	7	1			T9	1		T241	3		T242	2
auto[1]	values[4]	values[5]	6	1			T27	1		T236	3		T243	2
auto[1]	values[4]	values[6]	11	1			T11	1		T236	2		T233	1
auto[1]	values[4]	values[7]	12	1			T29	4		T35	1		T196	3
auto[1]	values[5]	values[0]	7	1			T24	2		T126	1		T130	4
auto[1]	values[5]	values[1]	4	1			T196	1		T218	1		T183	1
auto[1]	values[5]	values[2]	2	1			T180	1		T244	1		-	-
auto[1]	values[5]	values[3]	6	1			T29	1		T152	1		T245	2
auto[1]	values[5]	values[4]	2	1			T177	2		-	-		-	-
auto[1]	values[5]	values[5]	5	1			T24	2		T246	1		T242	2
auto[1]	values[5]	values[6]	10	1			T167	1		T172	2		T247	1
auto[1]	values[5]	values[7]	8	1			T8	1		T237	1		T248	2
auto[1]	values[6]	values[0]	3	1			T25	3		-	-		-	-
auto[1]	values[6]	values[1]	5	1			T177	1		T183	3		T249	1
auto[1]	values[6]	values[2]	14	1			T12	2		T192	2		T221	2
auto[1]	values[6]	values[3]	11	1			T9	1		T197	1		T224	1
auto[1]	values[6]	values[4]	6	1			T177	1		T250	4		T251	1
auto[1]	values[6]	values[5]	13	1			T11	1		T44	2		T234	1
auto[1]	values[6]	values[6]	5	1			T8	1		T34	1		T24	2
auto[1]	values[6]	values[7]	2	1			T182	1		T228	1		-	-
auto[1]	values[7]	values[0]	10	1			T178	1		T128	1		T252	2
auto[1]	values[7]	values[1]	5	1			T27	1		T34	3		T175	1
auto[1]	values[7]	values[2]	6	1			T230	1		T244	5		-	-
auto[1]	values[7]	values[3]	7	1			T34	1		T44	1		T152	2
auto[1]	values[7]	values[4]	11	1			T11	1		T24	1		T167	1
auto[1]	values[7]	values[5]	15	1			T11	6		T183	1		T237	4
auto[1]	values[7]	values[6]	3	1			T45	1		T253	2		-	-
auto[1]	values[7]	values[7]	6	1			T11	1		T165	1		T130	2