Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1791

1

T5

5

T6

1

T7

7

auto[1]

1760

1

T5

2

T7

4

T8

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1962

1

T5

7

T8

14

T16

17

auto[1]

1589

1

T6

1

T7

11

T15

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2802

1

T5

4

T6

1

T7

11

auto[1]

749

1

T5

3

T8

6

T16

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	683	1			T5	1		T7	2		T8	4
valid[1]	725	1			T7	3		T8	3		T15	2
valid[2]	688	1			T5	3		T7	2		T8	3
valid[3]	715	1			T5	2		T6	1		T7	2
valid[4]	740	1			T5	1		T7	2		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	125	1			T16	2		T17	1		T310	1
auto[0]	auto[0]	valid[0]	auto[1]	154	1			T7	2		T15	2		T42	4
auto[0]	auto[0]	valid[1]	auto[0]	110	1			T17	1		T29	1		T22	1
auto[0]	auto[0]	valid[1]	auto[1]	164	1			T7	2		T15	1		T18	1
auto[0]	auto[0]	valid[2]	auto[0]	123	1			T5	2		T8	1		T16	1
auto[0]	auto[0]	valid[2]	auto[1]	159	1			T17	1		T18	1		T42	1
auto[0]	auto[0]	valid[3]	auto[0]	117	1			T5	1		T16	1		T26	1
auto[0]	auto[0]	valid[3]	auto[1]	170	1			T6	1		T7	2		T18	1
auto[0]	auto[0]	valid[4]	auto[0]	132	1			T8	1		T16	1		T29	3
auto[0]	auto[0]	valid[4]	auto[1]	178	1			T7	1		T15	1		T18	2
auto[0]	auto[1]	valid[0]	auto[0]	116	1			T8	2		T29	1		T43	2
auto[0]	auto[1]	valid[0]	auto[1]	143	1			T18	3		T77	3		T79	2
auto[0]	auto[1]	valid[1]	auto[0]	113	1			T8	1		T16	1		T29	1
auto[0]	auto[1]	valid[1]	auto[1]	182	1			T7	1		T15	1		T17	1
auto[0]	auto[1]	valid[2]	auto[0]	123	1			T5	1		T16	2		T17	1
auto[0]	auto[1]	valid[2]	auto[1]	141	1			T7	2		T42	1		T77	3
auto[0]	auto[1]	valid[3]	auto[0]	127	1			T8	2		T16	3		T17	2
auto[0]	auto[1]	valid[3]	auto[1]	147	1			T15	2		T18	3		T42	1
auto[0]	auto[1]	valid[4]	auto[0]	127	1			T8	1		T16	1		T17	2
auto[0]	auto[1]	valid[4]	auto[1]	151	1			T7	1		T15	1		T18	1
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T5	1		T8	1		T29	2
auto[1]	auto[0]	valid[1]	auto[0]	64	1			T8	1		T16	1		T29	1
auto[1]	auto[0]	valid[2]	auto[0]	73	1			T8	1		T17	1		T29	1
auto[1]	auto[0]	valid[3]	auto[0]	70	1			T71	1		T64	1		T34	1
auto[1]	auto[0]	valid[4]	auto[0]	73	1			T5	1		T16	1		T43	1
auto[1]	auto[1]	valid[0]	auto[0]	66	1			T8	1		T17	1		T29	1
auto[1]	auto[1]	valid[1]	auto[0]	92	1			T8	1		T16	1		T17	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T8	1		T39	1		T64	1
auto[1]	auto[1]	valid[3]	auto[0]	84	1			T5	1		T17	1		T29	2
auto[1]	auto[1]	valid[4]	auto[0]	79	1			T16	2		T17	1		T29	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal