Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47994

1

T5

205

T8

243

T16

373

auto[1]

16319

1

T6

1

T7

11

T8

41

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46786

1

T5

138

T6

1

T7

11

auto[1]

17527

1

T5

67

T8

88

T16

128

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32971	1			T5	112		T6	1		T7	11
others[1]	5424	1			T5	16		T8	21		T16	30
others[2]	5481	1			T5	15		T8	24		T16	20
others[3]	6220	1			T5	19		T8	22		T16	36
interest[1]	3558	1			T5	12		T8	18		T16	26
interest[4]	21651	1			T5	76		T6	1		T7	11
interest[64]	10659	1			T5	31		T8	51		T16	61

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15563	1			T5	75		T8	80		T16	133
auto[0]	auto[0]	others[1]	2577	1			T5	12		T8	12		T16	19
auto[0]	auto[0]	others[2]	2653	1			T5	10		T8	14		T16	13
auto[0]	auto[0]	others[3]	2963	1			T5	14		T8	16		T16	23
auto[0]	auto[0]	interest[1]	1731	1			T5	8		T8	7		T16	19
auto[0]	auto[0]	interest[4]	10205	1			T5	51		T8	56		T16	84
auto[0]	auto[0]	interest[64]	4980	1			T5	19		T8	26		T16	38
auto[0]	auto[1]	others[0]	8468	1			T6	1		T7	11		T8	19
auto[0]	auto[1]	others[1]	1385	1			T8	2		T17	2		T42	18
auto[0]	auto[1]	others[2]	1318	1			T8	3		T17	3		T42	19
auto[0]	auto[1]	others[3]	1551	1			T17	6		T42	28		T22	6
auto[0]	auto[1]	interest[1]	875	1			T8	5		T17	2		T42	15
auto[0]	auto[1]	interest[4]	5622	1			T6	1		T7	11		T8	10
auto[0]	auto[1]	interest[64]	2722	1			T8	12		T17	10		T42	38
auto[1]	auto[0]	others[0]	8940	1			T5	37		T8	49		T16	67
auto[1]	auto[0]	others[1]	1462	1			T5	4		T8	7		T16	11
auto[1]	auto[0]	others[2]	1510	1			T5	5		T8	7		T16	7
auto[1]	auto[0]	others[3]	1706	1			T5	5		T8	6		T16	13
auto[1]	auto[0]	interest[1]	952	1			T5	4		T8	6		T16	7
auto[1]	auto[0]	interest[4]	5824	1			T5	25		T8	27		T16	43
auto[1]	auto[0]	interest[64]	2957	1			T5	12		T8	13		T16	23

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal