Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	853	1			T20	11		T38	14		T64	4
all_values[1]	853	1			T20	11		T38	14		T64	4
all_values[2]	853	1			T20	11		T38	14		T64	4
all_values[3]	853	1			T20	11		T38	14		T64	4
all_values[4]	853	1			T20	11		T38	14		T64	4
all_values[5]	853	1			T20	11		T38	14		T64	4
all_values[6]	853	1			T20	11		T38	14		T64	4
all_values[7]	853	1			T20	11		T38	14		T64	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3629

1

T20

45

T38

57

T64

23

auto[1]

3195

1

T20

43

T38

55

T64

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2768

1

T20

38

T38

32

T64

14

auto[1]

4056

1

T20

50

T38

80

T64

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3915

1

T20

49

T38

56

T64

20

auto[1]

2909

1

T20

39

T38

56

T64

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	144	1			T20	2		T38	1		T64	2
all_values[0]	auto[0]	auto[0]	auto[1]	91	1			T20	2		T38	1		T34	2
all_values[0]	auto[0]	auto[1]	auto[0]	143	1			T20	2		T63	1		T34	1
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T38	4		T63	1		T34	3
all_values[0]	auto[1]	auto[0]	auto[1]	225	1			T20	1		T38	5		T64	2
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T20	4		T38	3		T63	1
all_values[1]	auto[0]	auto[0]	auto[0]	208	1			T20	4		T38	2		T64	1
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T38	1		T64	1		T63	2
all_values[1]	auto[0]	auto[1]	auto[0]	130	1			T20	1		T38	2		T64	1
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T38	4		T34	2		T160	2
all_values[1]	auto[1]	auto[0]	auto[1]	213	1			T20	2		T38	2		T64	1
all_values[1]	auto[1]	auto[1]	auto[1]	148	1			T20	4		T38	3		T63	1
all_values[2]	auto[0]	auto[0]	auto[0]	196	1			T20	1		T38	2		T64	2
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T20	1		T38	1		T64	1
all_values[2]	auto[0]	auto[1]	auto[0]	141	1			T20	5		T38	3		T63	3
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T38	1		T34	1		T160	2
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T20	2		T38	5		T64	1
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T20	2		T38	2		T34	3
all_values[3]	auto[0]	auto[0]	auto[0]	173	1			T20	3		T38	3		T64	2
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T20	1		T38	2		T34	1
all_values[3]	auto[0]	auto[1]	auto[0]	171	1			T38	2		T63	1		T34	8
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T20	1		T38	1		T64	1
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T20	2		T38	1		T63	1
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T20	4		T38	5		T64	1
all_values[4]	auto[0]	auto[0]	auto[0]	172	1			T20	4		T38	1		T64	1
all_values[4]	auto[0]	auto[0]	auto[1]	72	1			T20	1		T38	1		T63	1
all_values[4]	auto[0]	auto[1]	auto[0]	176	1			T20	2		T38	3		T34	5
all_values[4]	auto[0]	auto[1]	auto[1]	79	1			T38	2		T64	1		T34	1
all_values[4]	auto[1]	auto[0]	auto[1]	184	1			T20	3		T38	6		T64	1
all_values[4]	auto[1]	auto[1]	auto[1]	170	1			T20	1		T38	1		T64	1
all_values[5]	auto[0]	auto[0]	auto[0]	246	1			T20	4		T38	5		T64	1
all_values[5]	auto[0]	auto[1]	auto[0]	265	1			T20	2		T38	3		T64	2
all_values[5]	auto[1]	auto[0]	auto[1]	178	1			T20	5		T38	3		T34	2
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T38	3		T64	1		T63	1
all_values[6]	auto[0]	auto[0]	auto[0]	160	1			T20	2		T38	1		T64	2
all_values[6]	auto[0]	auto[0]	auto[1]	97	1			T38	3		T64	1		T63	1
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T20	3		T38	2		T63	1
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T20	2		T38	1		T34	2
all_values[6]	auto[1]	auto[0]	auto[1]	194	1			T38	4		T64	1		T34	3
all_values[6]	auto[1]	auto[1]	auto[1]	179	1			T20	4		T38	3		T63	2
all_values[7]	auto[0]	auto[0]	auto[0]	167	1			T20	2		T63	1		T34	2
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T20	1		T64	1		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T20	1		T38	2		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T20	2		T38	2		T63	1
all_values[7]	auto[1]	auto[0]	auto[1]	205	1			T20	2		T38	7		T64	2
all_values[7]	auto[1]	auto[1]	auto[1]	180	1			T20	3		T38	3		T64	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal