Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2723399	1			T1	3		T4	1		T5	1
all_values[1]	2723399	1			T1	3		T4	1		T5	1
all_values[2]	2723399	1			T1	3		T4	1		T5	1
all_values[3]	2723399	1			T1	3		T4	1		T5	1
all_values[4]	2723399	1			T1	3		T4	1		T5	1
all_values[5]	2723399	1			T1	3		T4	1		T5	1
all_values[6]	2723399	1			T1	3		T4	1		T5	1
all_values[7]	2723399	1			T1	3		T4	1		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20782618

1

T1

24

T4

8

T5

8

auto[1]

1004574

1

T30

38

T42

79

T44

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21765270

1

T1

24

T4

8

T5

8

auto[1]

21922

1

T7

2

T19

104

T22

64

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2479654	1			T1	3		T4	1		T5	1
all_values[0]	auto[0]	auto[1]	10872	1			T19	64		T22	32		T28	80
all_values[0]	auto[1]	auto[0]	232078	1			T30	4		T42	4		T44	1
all_values[0]	auto[1]	auto[1]	795	1			T30	5		T42	3		T72	4
all_values[1]	auto[0]	auto[0]	2623709	1			T1	3		T4	1		T5	1
all_values[1]	auto[0]	auto[1]	5523	1			T19	40		T22	32		T28	13
all_values[1]	auto[1]	auto[0]	93896	1			T42	3		T44	1		T72	6
all_values[1]	auto[1]	auto[1]	271	1			T42	3		T72	3		T73	5
all_values[2]	auto[0]	auto[0]	2557575	1			T1	3		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	2257	1			T30	4		T38	33		T43	31
all_values[2]	auto[1]	auto[0]	163307	1			T30	1		T42	6		T44	3
all_values[2]	auto[1]	auto[1]	260	1			T30	2		T42	4		T44	2
all_values[3]	auto[0]	auto[0]	2630415	1			T1	3		T4	1		T5	1
all_values[3]	auto[0]	auto[1]	202	1			T42	5		T72	5		T269	1
all_values[3]	auto[1]	auto[0]	92593	1			T42	3		T44	2		T72	1
all_values[3]	auto[1]	auto[1]	189	1			T30	2		T42	6		T44	3
all_values[4]	auto[0]	auto[0]	2667339	1			T1	3		T4	1		T5	1
all_values[4]	auto[0]	auto[1]	167	1			T42	5		T44	1		T72	4
all_values[4]	auto[1]	auto[0]	55691	1			T30	8		T42	9		T72	1
all_values[4]	auto[1]	auto[1]	202	1			T42	6		T72	2		T73	5
all_values[5]	auto[0]	auto[0]	2601526	1			T1	3		T4	1		T5	1
all_values[5]	auto[0]	auto[1]	285	1			T7	2		T50	2		T270	6
all_values[5]	auto[1]	auto[0]	121427	1			T30	7		T42	12		T44	3
all_values[5]	auto[1]	auto[1]	161	1			T30	3		T42	2		T44	3
all_values[6]	auto[0]	auto[0]	2580363	1			T1	3		T4	1		T5	1
all_values[6]	auto[0]	auto[1]	188	1			T30	1		T42	7		T72	4
all_values[6]	auto[1]	auto[0]	142662	1			T30	1		T42	6		T72	2
all_values[6]	auto[1]	auto[1]	186	1			T30	2		T42	4		T72	1
all_values[7]	auto[0]	auto[0]	2622343	1			T1	3		T4	1		T5	1
all_values[7]	auto[0]	auto[1]	200	1			T30	2		T42	8		T44	1
all_values[7]	auto[1]	auto[0]	100692	1			T30	1		T42	4		T44	4
all_values[7]	auto[1]	auto[1]	164	1			T30	2		T42	4		T72	2