Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	25049	1			T4	12		T5	2		T6	2
auto[SpiFlashAddrCfg]	6181	1			T1	3		T6	4		T9	2
auto[SpiFlashAddr3b]	7227	1			T6	4		T9	2		T14	64
auto[SpiFlashAddr4b]	6025	1			T6	10		T14	57		T31	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25742

1

T1

3

T4

12

T5

2

auto[1]

18740

1

T6

20

T9

4

T14

240

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23843

1

T4

12

T5

2

T6

8

auto[1]

20639

1

T1

3

T6

12

T11

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	28782	1			T4	12		T5	2		T6	8
values[1]	840	1			T14	7		T31	4		T24	2
values[2]	1176	1			T6	4		T14	10		T24	2
values[3]	1170	1			T6	6		T14	6		T33	2
values[4]	1188	1			T1	1		T11	2		T14	20
values[5]	1215	1			T14	13		T31	6		T24	8
values[6]	1096	1			T14	12		T24	9		T19	4
values[7]	1107	1			T14	12		T24	5		T19	2
values[8]	7908	1			T1	2		T6	2		T9	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24405

1

T4

12

T5

2

T6

20

auto[1]

20077

1

T1

3

T14

495

T19

115

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

42798

1

T1

3

T4

12

T5

2

write

1684

1

T14

20

T31

4

T24

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15836

1

T1

1

T6

10

T9

4

valids[0x1]

28646

1

T1

2

T4

12

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1228	1			T4	6		T6	2		T13	4
internal_process_ops[0x5a]	1281	1			T6	2		T14	15		T31	2
internal_process_ops[0x05]	14203	1			T4	2		T5	2		T14	224
internal_process_ops[0x35]	1207	1			T4	4		T14	12		T24	4
internal_process_ops[0x15]	1261	1			T13	4		T14	10		T33	2
internal_process_ops[0x03]	894	1			T14	6		T33	2		T24	2
internal_process_ops[0x0b]	873	1			T1	2		T11	2		T14	5
internal_process_ops[0x3b]	858	1			T1	1		T14	1		T24	7
internal_process_ops[0x6b]	831	1			T14	2		T24	4		T19	1
internal_process_ops[0xbb]	910	1			T6	4		T14	4		T24	4
internal_process_ops[0xeb]	958	1			T6	2		T11	2		T14	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43671

1

T1

3

T4

12

T5

2

auto[1]

811

1

T14

8

T31

4

T24

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42930

1

T1

3

T4

12

T5

2

auto[1]

1552

1

T14

18

T24

4

T19

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8028

1

T4

12

T5

2

T12

20

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4482

1

T6

2

T33

2

T24

57

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1869

1

T11

6

T24

17

T37

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1628

1

T6

4

T9

2

T31

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2240

1

T24

11

T35

6

T37

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1864

1

T6

4

T9

2

T31

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1819

1

T24

8

T39

2

T205

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1586

1

T6

10

T31

4

T33

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

72

1

T36

2

T38

1

T207

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

66

1

T36

3

T42

2

T38

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

48

1

T43

1

T167

1

T44

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

54

1

T31

4

T38

3

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

55

1

T24

1

T36

3

T45

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

49

1

T38

2

T167

2

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

45

1

T42

1

T38

2

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

61

1

T34

1

T36

1

T190

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

68

1

T167

4

T263

2

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

47

1

T24

1

T42

2

T38

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

36

1

T36

1

T166

1

T184

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

60

1

T34

2

T36

2

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

72

1

T36

2

T42

2

T44

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

44

1

T44

1

T45

2

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

59

1

T34

1

T36

1

T167

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

53

1

T43

3

T45

1

T47

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7236

1

T14

158

T19

45

T20

12

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4888

1

T14

147

T19

10

T20

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1187

1

T1

3

T14

31

T19

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1075

1

T14

28

T19

9

T20

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1376

1

T14

30

T19

17

T20

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1344

1

T14

31

T19

11

T20

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1119

1

T14

25

T19

6

T20

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1057

1

T14

25

T19

4

T20

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

48

1

T14

2

T28

1

T51

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

38

1

T28

2

T30

2

T67

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

53

1

T14

1

T28

2

T30

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

36

1

T19

1

T44

1

T264

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

46

1

T30

1

T265

1

T79

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

43

1

T14

4

T20

1

T28

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

75

1

T14

3

T51

1

T266

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

48

1

T266

1

T86

1

T267

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

64

1

T14

1

T22

3

T266

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

54

1

T19

1

T266

1

T268

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

29

1

T14

2

T28

1

T51

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

45

1

T19

1

T51

1

T265

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

50

1

T14

1

T19

1

T268

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

52

1

T14

3

T20

1

T28

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

53

1

T14

2

T28

1

T266

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

61

1

T14

1

T19

1

T72

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3512	1			T12	20		T24	31		T37	6
auto[0]	values[0]	valids[0x1]	11387	1			T4	12		T5	2		T6	8
auto[0]	values[1]	valids[0x1]	469	1			T31	4		T24	2		T34	1
auto[0]	values[2]	valids[0x0]	479	1			T6	4		T24	1		T34	1
auto[0]	values[2]	valids[0x1]	242	1			T24	1		T36	12		T38	2
auto[0]	values[3]	valids[0x0]	460	1			T6	6		T33	2		T24	2
auto[0]	values[3]	valids[0x1]	235	1			T24	2		T41	2		T34	1
auto[0]	values[4]	valids[0x0]	462	1			T24	3		T34	3		T36	5
auto[0]	values[4]	valids[0x1]	221	1			T11	2		T24	4		T34	2
auto[0]	values[5]	valids[0x0]	531	1			T31	4		T24	8		T34	6
auto[0]	values[5]	valids[0x1]	207	1			T31	2		T41	2		T34	1
auto[0]	values[6]	valids[0x0]	453	1			T24	6		T205	2		T154	2
auto[0]	values[6]	valids[0x1]	255	1			T24	3		T34	1		T36	7
auto[0]	values[7]	valids[0x0]	462	1			T24	4		T36	2		T42	6
auto[0]	values[7]	valids[0x1]	231	1			T24	1		T205	2		T34	1
auto[0]	values[8]	valids[0x0]	3011	1			T9	4		T11	4		T31	2
auto[0]	values[8]	valids[0x1]	1788	1			T6	2		T33	6		T24	15
auto[1]	values[0]	valids[0x0]	2980	1			T14	53		T19	32		T20	12
auto[1]	values[0]	valids[0x1]	10903	1			T14	313		T19	43		T20	14
auto[1]	values[1]	valids[0x1]	371	1			T14	7		T20	2		T28	6
auto[1]	values[2]	valids[0x0]	274	1			T14	7		T19	1		T28	2
auto[1]	values[2]	valids[0x1]	181	1			T14	3		T28	1		T30	2
auto[1]	values[3]	valids[0x0]	272	1			T14	4		T19	3		T28	3
auto[1]	values[3]	valids[0x1]	203	1			T14	2		T19	2		T28	2
auto[1]	values[4]	valids[0x0]	312	1			T1	1		T14	7		T19	1
auto[1]	values[4]	valids[0x1]	193	1			T14	13		T19	3		T22	2
auto[1]	values[5]	valids[0x0]	269	1			T14	9		T19	1		T20	2
auto[1]	values[5]	valids[0x1]	208	1			T14	4		T19	5		T28	9
auto[1]	values[6]	valids[0x0]	234	1			T14	8		T19	1		T108	1
auto[1]	values[6]	valids[0x1]	154	1			T14	4		T19	3		T51	3
auto[1]	values[7]	valids[0x0]	238	1			T14	8		T19	1		T49	1
auto[1]	values[7]	valids[0x1]	176	1			T14	4		T19	1		T28	3
auto[1]	values[8]	valids[0x0]	1887	1			T14	26		T19	9		T20	6
auto[1]	values[8]	valids[0x1]	1222	1			T1	2		T14	23		T19	9