Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2878168

1

T1

77

T4

13220

T5

6894

auto[1]

12965

1

T14

215

T24

93

T19

15

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875173

1

T1

77

T4

7792

T5

6894

auto[1]

2015960

1

T4

5428

T13

3280

T14

6333

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	617877	1			T1	47		T4	3151		T5	209
auto[524288:1048575]	308737	1			T4	952		T5	432		T13	2479
auto[1048576:1572863]	325538	1			T4	924		T5	1166		T12	9
auto[1572864:2097151]	315712	1			T1	30		T5	2		T12	6
auto[2097152:2621439]	323190	1			T4	1		T5	458		T12	617
auto[2621440:3145727]	361742	1			T4	4771		T12	679		T14	1063
auto[3145728:3670015]	307573	1			T4	402		T5	1253		T12	295
auto[3670016:4194303]	330764	1			T4	3019		T5	3374		T12	296

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2033975

1

T1

5

T4

5464

T5

18

auto[1]

857158

1

T1

72

T4

7756

T5

6876

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2534965

1

T1

77

T4

13220

T5

6894

auto[1]

356168

1

T12

1561

T14

802

T24

10

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	200034	1			T1	47		T4	1902		T5	209
auto[0]	auto[0]	auto[0:524287]	auto[1]	364909	1			T4	1249		T13	1633		T14	1274
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	77275	1			T4	952		T5	432		T13	2479
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	187557	1			T14	1385		T24	2704		T28	1038
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	116785	1			T4	924		T5	1166		T12	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	176310	1			T13	14		T14	384		T24	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	80539	1			T1	30		T5	2		T12	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	166375	1			T13	6		T14	326		T24	259
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	98430	1			T4	1		T5	458		T12	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	172505	1			T13	1627		T14	812		T24	2838
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	111639	1			T4	2796		T12	49		T14	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	212728	1			T4	1975		T14	646		T24	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	87688	1			T4	395		T5	1253		T12	295
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	187707	1			T4	7		T14	7		T24	3325
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	94174	1			T4	822		T5	3374		T12	296
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	189646	1			T4	2197		T14	514		T22	3106
auto[0]	auto[1]	auto[0:524287]	auto[0]	2715	1			T12	314		T14	3		T24	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	47620	1			T19	645		T22	512		T36	4675
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	264	1			T19	3		T156	5		T34	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	42340	1			T43	813		T167	1		T72	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	706	1			T12	1		T24	1		T28	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	30194	1			T28	261		T30	2626		T266	259
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	323	1			T28	4		T51	1		T34	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	66657	1			T28	2117		T34	129		T67	385
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	836	1			T12	616		T14	1		T20	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	50378	1			T20	726		T51	198		T67	2479
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	806	1			T12	630		T14	5		T24	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	34827	1			T14	387		T24	4		T28	621
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	666	1			T19	2		T28	1		T30	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	30107	1			T19	130		T28	128		T30	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	741	1			T14	5		T20	1		T28	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	44687	1			T14	401		T20	512		T67	517
auto[1]	auto[0]	auto[0:524287]	auto[0]	227	1			T14	1		T19	2		T30	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	1933	1			T14	2		T19	5		T30	6
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	137	1			T14	4		T28	2		T51	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	974	1			T14	54		T28	10		T51	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	146	1			T24	2		T38	3		T43	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1092	1			T24	62		T38	7		T43	19
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	159	1			T14	5		T19	1		T28	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1310	1			T14	45		T19	4		T28	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	127	1			T14	4		T20	1		T51	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	702	1			T14	53		T51	1		T42	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	163	1			T14	2		T24	2		T36	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1169	1			T14	15		T24	27		T36	65
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	146	1			T30	1		T36	2		T38	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1104	1			T36	56		T38	1		T266	22
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	157	1			T14	2		T22	4		T28	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1118	1			T14	28		T22	4		T28	37
auto[1]	auto[1]	auto[0:524287]	auto[0]	37	1			T36	1		T266	1		T86	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	402	1			T36	23		T266	7		T86	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	39	1			T167	1		T72	1		T294	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	151	1			T72	1		T294	1		T192	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	33	1			T30	1		T266	2		T268	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	272	1			T30	4		T266	33		T44	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	54	1			T28	1		T34	1		T67	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	295	1			T34	3		T67	24		T72	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	37	1			T268	3		T190	1		T166	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	175	1			T268	2		T190	1		T166	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	27	1			T51	1		T265	1		T294	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	383	1			T265	7		T294	65		T80	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	22	1			T19	2		T36	2		T190	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	133	1			T19	1		T36	3		T190	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	41	1			T266	1		T79	2		T45	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	200	1			T266	11		T79	23		T45	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1672812	1			T1	5		T4	5464		T5	18
auto[0]	auto[0]	auto[1]	851489	1			T1	72		T4	7756		T5	6876
auto[0]	auto[1]	auto[0]	348518	1			T12	11		T14	802		T24	10
auto[0]	auto[1]	auto[1]	5349	1			T12	1550		T156	1		T266	1
auto[1]	auto[0]	auto[0]	10407	1			T14	203		T24	93		T19	12
auto[1]	auto[0]	auto[1]	257	1			T14	12		T28	1		T30	1
auto[1]	auto[1]	auto[0]	2238	1			T19	3		T28	1		T30	5
auto[1]	auto[1]	auto[1]	63	1			T67	1		T36	2		T268	1