Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14429

1

T4

12

T5

2

T12

20

auto[1]

9976

1

T6

20

T9

4

T31

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3191	1			T4	12		T24	55		T154	16
values[1]	3060	1			T31	16		T24	43		T205	4
values[2]	2864	1			T24	20		T39	6		T34	20
values[3]	2850	1			T5	2		T9	4		T12	20
values[4]	3774	1			T6	20		T13	8		T24	95
values[5]	2837	1			T33	16		T156	22		T42	20
values[6]	3266	1			T41	14		T35	10		T99	4
values[7]	2563	1			T11	6		T42	22		T43	102

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3569	1			T5	2		T12	20		T11	6
values[1]	2886	1			T33	16		T99	4		T155	10
values[2]	3078	1			T24	75		T34	24		T36	20
values[3]	2614	1			T36	101		T42	60		T38	20
values[4]	2804	1			T6	20		T24	43		T35	10
values[5]	3072	1			T34	20		T36	89		T38	63
values[6]	3188	1			T31	16		T205	4		T154	16
values[7]	3194	1			T4	12		T9	4		T13	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	358	1			T222	4		T192	26		T180	4
auto[0]	values[0]	values[1]	172	1			T209	18		T185	11		T261	12
auto[0]	values[0]	values[2]	110	1			T217	2		T238	10		T240	15
auto[0]	values[0]	values[3]	193	1			T36	15		T45	12		T166	17
auto[0]	values[0]	values[4]	186	1			T45	10		T162	14		T305	8
auto[0]	values[0]	values[5]	277	1			T34	7		T167	14		T47	7
auto[0]	values[0]	values[6]	285	1			T154	16		T36	14		T38	12
auto[0]	values[0]	values[7]	249	1			T4	12		T24	24		T79	14
auto[0]	values[1]	values[0]	203	1			T157	2		T178	16		T45	14
auto[0]	values[1]	values[1]	150	1			T155	10		T45	13		T306	20
auto[0]	values[1]	values[2]	152	1			T36	15		T80	18		T192	13
auto[0]	values[1]	values[3]	314	1			T36	70		T167	13		T45	16
auto[0]	values[1]	values[4]	162	1			T24	12		T261	15		T307	6
auto[0]	values[1]	values[5]	254	1			T199	16		T44	7		T45	20
auto[0]	values[1]	values[6]	422	1			T205	4		T36	15		T167	21
auto[0]	values[1]	values[7]	248	1			T38	14		T79	8		T212	10
auto[0]	values[2]	values[0]	225	1			T211	18		T201	4		T239	21
auto[0]	values[2]	values[1]	146	1			T36	14		T162	21		T179	14
auto[0]	values[2]	values[2]	390	1			T43	46		T165	12		T190	24
auto[0]	values[2]	values[3]	218	1			T43	12		T47	14		T188	10
auto[0]	values[2]	values[4]	135	1			T39	6		T34	9		T36	8
auto[0]	values[2]	values[5]	205	1			T38	11		T204	4		T186	18
auto[0]	values[2]	values[6]	131	1			T44	15		T220	2		T185	12
auto[0]	values[2]	values[7]	180	1			T24	13		T190	15		T212	26
auto[0]	values[3]	values[0]	293	1			T5	2		T12	20		T37	18
auto[0]	values[3]	values[1]	134	1			T44	10		T212	15		T184	12
auto[0]	values[3]	values[2]	340	1			T162	12		T80	23		T196	10
auto[0]	values[3]	values[3]	161	1			T42	17		T215	4		T192	13
auto[0]	values[3]	values[4]	190	1			T43	12		T184	17		T80	10
auto[0]	values[3]	values[5]	98	1			T36	12		T207	2		T191	8
auto[0]	values[3]	values[6]	163	1			T36	15		T185	12		T308	12
auto[0]	values[3]	values[7]	232	1			T34	12		T173	5		T194	8
auto[0]	values[4]	values[0]	313	1			T24	9		T203	47		T171	12
auto[0]	values[4]	values[1]	264	1			T38	32		T46	12		T184	13
auto[0]	values[4]	values[2]	457	1			T24	69		T34	10		T42	125
auto[0]	values[4]	values[3]	291	1			T38	10		T163	6		T91	22
auto[0]	values[4]	values[4]	264	1			T38	14		T164	29		T190	22
auto[0]	values[4]	values[5]	221	1			T38	11		T214	10		T190	34
auto[0]	values[4]	values[6]	288	1			T36	7		T216	19		T211	22
auto[0]	values[4]	values[7]	239	1			T13	8		T40	12		T92	8
auto[0]	values[5]	values[0]	132	1			T43	10		T53	13		T309	10
auto[0]	values[5]	values[1]	250	1			T44	13		T45	13		T166	17
auto[0]	values[5]	values[2]	175	1			T190	10		T173	12		T192	18
auto[0]	values[5]	values[3]	271	1			T42	12		T45	11		T80	14
auto[0]	values[5]	values[4]	166	1			T310	8		T211	10		T150	23
auto[0]	values[5]	values[5]	146	1			T79	12		T189	2		T200	10
auto[0]	values[5]	values[6]	213	1			T156	22		T38	7		T239	39
auto[0]	values[5]	values[7]	228	1			T194	13		T187	16		T211	9
auto[0]	values[6]	values[0]	239	1			T38	11		T172	8		T173	12
auto[0]	values[6]	values[1]	201	1			T219	10		T47	17		T187	8
auto[0]	values[6]	values[2]	211	1			T44	31		T239	15		T169	17
auto[0]	values[6]	values[3]	159	1			T42	13		T43	29		T47	23
auto[0]	values[6]	values[4]	333	1			T35	10		T167	18		T263	24
auto[0]	values[6]	values[5]	326	1			T43	14		T47	24		T173	13
auto[0]	values[6]	values[6]	225	1			T212	15		T188	12		T216	15
auto[0]	values[6]	values[7]	245	1			T166	13		T238	10		T311	18
auto[0]	values[7]	values[0]	417	1			T11	6		T43	57		T312	8
auto[0]	values[7]	values[1]	223	1			T42	14		T43	9		T44	8
auto[0]	values[7]	values[2]	117	1			T313	2		T88	17		T247	19
auto[0]	values[7]	values[3]	76	1			T192	16		T314	16		T315	8
auto[0]	values[7]	values[4]	176	1			T43	13		T193	16		T221	18
auto[0]	values[7]	values[5]	177	1			T45	13		T186	12		T46	10
auto[0]	values[7]	values[6]	160	1			T181	22		T47	7		T150	11
auto[0]	values[7]	values[7]	250	1			T183	14		T174	4		T213	10
auto[1]	values[0]	values[0]	158	1			T192	20		T261	10		T200	8
auto[1]	values[0]	values[1]	196	1			T185	36		T261	8		T200	12
auto[1]	values[0]	values[2]	96	1			T238	11		T240	5		T55	6
auto[1]	values[0]	values[3]	156	1			T36	5		T45	8		T296	14
auto[1]	values[0]	values[4]	148	1			T45	10		T162	6		T211	9
auto[1]	values[0]	values[5]	289	1			T34	13		T167	6		T47	22
auto[1]	values[0]	values[6]	151	1			T36	11		T38	22		T186	11
auto[1]	values[0]	values[7]	167	1			T24	31		T79	6		T316	12
auto[1]	values[1]	values[0]	175	1			T45	9		T46	5		T260	16
auto[1]	values[1]	values[1]	106	1			T45	7		T239	7		T235	23
auto[1]	values[1]	values[2]	117	1			T36	5		T80	7		T192	7
auto[1]	values[1]	values[3]	64	1			T36	11		T167	7		T45	8
auto[1]	values[1]	values[4]	86	1			T24	31		T261	5		T238	7
auto[1]	values[1]	values[5]	289	1			T44	13		T45	8		T47	17
auto[1]	values[1]	values[6]	212	1			T31	16		T36	66		T167	27
auto[1]	values[1]	values[7]	106	1			T38	6		T79	12		T212	13
auto[1]	values[2]	values[0]	121	1			T211	9		T239	41		T317	4
auto[1]	values[2]	values[1]	89	1			T36	6		T162	2		T244	14
auto[1]	values[2]	values[2]	222	1			T43	10		T190	38		T80	11
auto[1]	values[2]	values[3]	148	1			T43	8		T47	6		T188	13
auto[1]	values[2]	values[4]	218	1			T34	11		T36	12		T46	7
auto[1]	values[2]	values[5]	127	1			T38	32		T186	2		T238	12
auto[1]	values[2]	values[6]	78	1			T44	7		T185	8		T175	11
auto[1]	values[2]	values[7]	231	1			T24	7		T190	42		T212	5
auto[1]	values[3]	values[0]	140	1			T36	6		T44	11		T186	13
auto[1]	values[3]	values[1]	83	1			T44	17		T212	5		T184	8
auto[1]	values[3]	values[2]	161	1			T162	8		T80	7		T187	7
auto[1]	values[3]	values[3]	95	1			T42	3		T192	11		T177	9
auto[1]	values[3]	values[4]	93	1			T43	8		T184	6		T80	11
auto[1]	values[3]	values[5]	142	1			T36	77		T80	18		T188	12
auto[1]	values[3]	values[6]	214	1			T36	27		T185	8		T169	27
auto[1]	values[3]	values[7]	311	1			T9	4		T34	8		T173	17
auto[1]	values[4]	values[0]	244	1			T24	11		T166	15		T173	11
auto[1]	values[4]	values[1]	244	1			T38	47		T46	29		T184	7
auto[1]	values[4]	values[2]	196	1			T24	6		T34	14		T42	34
auto[1]	values[4]	values[3]	144	1			T38	10		T79	7		T184	8
auto[1]	values[4]	values[4]	186	1			T6	20		T38	6		T190	3
auto[1]	values[4]	values[5]	185	1			T38	9		T190	10		T80	12
auto[1]	values[4]	values[6]	163	1			T36	13		T216	7		T211	5
auto[1]	values[4]	values[7]	75	1			T188	10		T200	6		T238	12
auto[1]	values[5]	values[0]	134	1			T43	10		T318	14		T53	8
auto[1]	values[5]	values[1]	175	1			T33	16		T44	7		T45	9
auto[1]	values[5]	values[2]	152	1			T190	43		T173	9		T192	6
auto[1]	values[5]	values[3]	219	1			T42	8		T182	12		T45	25
auto[1]	values[5]	values[4]	165	1			T211	10		T150	10		T227	15
auto[1]	values[5]	values[5]	75	1			T79	8		T200	11		T53	4
auto[1]	values[5]	values[6]	127	1			T38	13		T239	7		T319	3
auto[1]	values[5]	values[7]	209	1			T194	34		T187	4		T211	11
auto[1]	values[6]	values[0]	219	1			T41	14		T38	9		T173	11
auto[1]	values[6]	values[1]	247	1			T99	4		T47	57		T187	12
auto[1]	values[6]	values[2]	87	1			T44	15		T239	5		T169	11
auto[1]	values[6]	values[3]	65	1			T42	7		T43	12		T47	6
auto[1]	values[6]	values[4]	242	1			T167	6		T47	11		T173	11
auto[1]	values[6]	values[5]	165	1			T43	39		T47	10		T173	9
auto[1]	values[6]	values[6]	190	1			T212	5		T188	11		T216	13
auto[1]	values[6]	values[7]	112	1			T166	7		T238	10		T25	13
auto[1]	values[7]	values[0]	198	1			T43	5		T45	26		T47	14
auto[1]	values[7]	values[1]	206	1			T42	8		T43	11		T44	12
auto[1]	values[7]	values[2]	95	1			T320	8		T88	6		T247	8
auto[1]	values[7]	values[3]	40	1			T192	6		T60	8		T252	11
auto[1]	values[7]	values[4]	54	1			T43	7		T46	8		T321	5
auto[1]	values[7]	values[5]	96	1			T45	7		T186	17		T46	10
auto[1]	values[7]	values[6]	166	1			T47	26		T168	14		T150	9
auto[1]	values[7]	values[7]	112	1			T241	7		T285	10		T228	13