Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	343	1			T24	3		T34	2		T36	3
auto[ReadAddrCrossIntoMailbox]	267	1			T24	2		T34	1		T36	4
auto[ReadAddrCrossOutOfMailbox]	278	1			T24	3		T34	3		T36	8
auto[ReadAddrCrossAllMailbox]	162	1			T24	1		T36	4		T42	3
auto[ReadAddrOutsideMailbox]	3074	1			T6	6		T11	4		T31	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1997

1

T6

3

T11

2

T31

1

auto[1]

2127

1

T6

3

T11

2

T31

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	692	1			T33	2		T24	2		T41	2
read_ops[0x0b]	668	1			T11	2		T33	2		T24	3
read_ops[0x3b]	654	1			T24	7		T155	2		T34	4
read_ops[0x6b]	652	1			T24	4		T99	2		T154	2
read_ops[0xbb]	716	1			T6	4		T24	4		T154	2
read_ops[0xeb]	742	1			T6	2		T11	2		T31	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T42	1		T167	1		T44	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T36	1		T46	1		T234	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T38	1		T44	1		T162	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T167	1		T173	1		T188	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T38	1		T43	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T167	1		T44	1		T45	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T241	2		T228	1		T124	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T173	1		T239	1		T88	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	251	1			T33	1		T24	1		T41	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T33	1		T24	1		T41	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T165	1		T186	1		T190	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T36	1		T42	1		T165	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T44	1		T45	1		T190	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T24	1		T36	1		T79	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T38	1		T44	1		T183	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T36	3		T38	1		T167	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T42	1		T184	1		T124	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T45	1		T46	1		T173	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	249	1			T11	1		T33	1		T41	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	235	1			T11	1		T33	1		T24	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T167	1		T79	1		T46	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T34	1		T38	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T36	1		T183	1		T45	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T183	1		T212	1		T187	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T24	1		T43	1		T79	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T24	1		T167	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T42	1		T190	1		T166	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T24	1		T38	1		T47	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	229	1			T24	1		T155	1		T36	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T24	3		T155	1		T34	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T38	1		T173	1		T192	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T24	1		T38	1		T167	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T38	1		T43	1		T45	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T43	1		T167	2		T190	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T34	1		T36	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T24	1		T36	1		T38	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T46	1		T192	2		T321	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T167	1		T238	1		T239	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	212	1			T99	1		T154	1		T36	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T24	2		T99	1		T154	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T34	1		T167	1		T183	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T24	1		T44	3		T183	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T167	1		T79	1		T46	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T36	1		T42	1		T45	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T44	1		T45	2		T46	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T36	1		T46	1		T190	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T36	1		T162	1		T194	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T36	1		T44	1		T150	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T6	2		T24	2		T154	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T6	2		T24	1		T154	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T24	1		T42	1		T167	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T36	1		T45	2		T80	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T36	1		T167	2		T162	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T24	1		T34	1		T42	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T36	1		T42	1		T167	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T34	2		T36	1		T42	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T38	1		T173	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T36	2		T42	1		T44	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T6	1		T11	1		T31	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T6	1		T11	1		T31	1