Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2723399	1			T1	3		T4	1		T5	1
all_pins[1]	2723399	1			T1	3		T4	1		T5	1
all_pins[2]	2723399	1			T1	3		T4	1		T5	1
all_pins[3]	2723399	1			T1	3		T4	1		T5	1
all_pins[4]	2723399	1			T1	3		T4	1		T5	1
all_pins[5]	2723399	1			T1	3		T4	1		T5	1
all_pins[6]	2723399	1			T1	3		T4	1		T5	1
all_pins[7]	2723399	1			T1	3		T4	1		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21639641	1			T1	24		T4	8		T5	8
values[0x1]	147551	1			T30	16		T42	32		T44	8
transitions[0x0=>0x1]	145975	1			T30	14		T42	23		T44	6
transitions[0x1=>0x0]	145982	1			T30	14		T42	23		T44	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2722522	1			T1	3		T4	1		T5	1
all_pins[0]	values[0x1]	877	1			T30	5		T42	3		T72	4
all_pins[0]	transitions[0x0=>0x1]	751	1			T30	5		T42	3		T72	4
all_pins[0]	transitions[0x1=>0x0]	166	1			T42	3		T72	3		T73	2
all_pins[1]	values[0x0]	2723107	1			T1	3		T4	1		T5	1
all_pins[1]	values[0x1]	292	1			T42	3		T72	3		T73	5
all_pins[1]	transitions[0x0=>0x1]	207	1			T42	2		T72	2		T73	3
all_pins[1]	transitions[0x1=>0x0]	188	1			T30	2		T42	3		T44	2
all_pins[2]	values[0x0]	2723126	1			T1	3		T4	1		T5	1
all_pins[2]	values[0x1]	273	1			T30	2		T42	4		T44	2
all_pins[2]	transitions[0x0=>0x1]	224	1			T30	1		T42	3		T72	3
all_pins[2]	transitions[0x1=>0x0]	140	1			T30	1		T42	5		T44	1
all_pins[3]	values[0x0]	2723210	1			T1	3		T4	1		T5	1
all_pins[3]	values[0x1]	189	1			T30	2		T42	6		T44	3
all_pins[3]	transitions[0x0=>0x1]	133	1			T30	2		T42	3		T44	3
all_pins[3]	transitions[0x1=>0x0]	146	1			T42	3		T73	5		T162	2
all_pins[4]	values[0x0]	2723197	1			T1	3		T4	1		T5	1
all_pins[4]	values[0x1]	202	1			T42	6		T72	2		T73	5
all_pins[4]	transitions[0x0=>0x1]	161	1			T42	5		T72	2		T73	2
all_pins[4]	transitions[0x1=>0x0]	3153	1			T30	3		T42	1		T44	3
all_pins[5]	values[0x0]	2720205	1			T1	3		T4	1		T5	1
all_pins[5]	values[0x1]	3194	1			T30	3		T42	2		T44	3
all_pins[5]	transitions[0x0=>0x1]	2061	1			T30	3		T42	1		T44	3
all_pins[5]	transitions[0x1=>0x0]	141227	1			T30	2		T42	3		T72	1
all_pins[6]	values[0x0]	2581039	1			T1	3		T4	1		T5	1
all_pins[6]	values[0x1]	142360	1			T30	2		T42	4		T72	1
all_pins[6]	transitions[0x0=>0x1]	142322	1			T30	1		T42	3		T72	1
all_pins[6]	transitions[0x1=>0x0]	126	1			T30	1		T42	3		T72	2
all_pins[7]	values[0x0]	2723235	1			T1	3		T4	1		T5	1
all_pins[7]	values[0x1]	164	1			T30	2		T42	4		T72	2
all_pins[7]	transitions[0x0=>0x1]	116	1			T30	2		T42	3		T72	2
all_pins[7]	transitions[0x1=>0x0]	836	1			T30	5		T42	2		T72	4