Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	3	125	97.66

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	3	125	97.66	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3083	1			T37	18		T42	39		T38	20
values[1]	3209	1			T4	12		T12	20		T24	29
values[2]	2705	1			T9	4		T35	10		T39	6
values[3]	3212	1			T156	22		T157	2		T34	40
values[4]	3368	1			T13	8		T24	101		T41	14
values[5]	3079	1			T11	6		T31	16		T24	43
values[6]	2517	1			T6	20		T154	16		T36	25
values[7]	3232	1			T5	2		T33	16		T24	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3475	1			T4	12		T6	20		T24	43
values[1]	2855	1			T5	2		T34	24		T42	40
values[2]	2797	1			T41	14		T157	2		T36	40
values[3]	3441	1			T11	6		T31	16		T24	104
values[4]	2848	1			T35	10		T37	18		T36	134
values[5]	3330	1			T33	16		T24	40		T154	16
values[6]	3128	1			T13	8		T99	4		T39	6
values[7]	2531	1			T9	4		T12	20		T24	26

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23971

1

T4

12

T5

2

T6

20

auto[1]

434

1

T31

4

T24

1

T34

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	3	125	97.66	3

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[2]]	0	1	1
[auto[1]]	[values[4]]	[values[2]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	553	1			T163	6		T164	29		T46	41
auto[0]	values[0]	values[1]	278	1			T165	12		T47	27		T166	49
auto[0]	values[0]	values[2]	351	1			T42	38		T38	20		T167	20
auto[0]	values[0]	values[3]	451	1			T47	63		T168	12		T169	21
auto[0]	values[0]	values[4]	384	1			T37	18		T45	20		T170	12
auto[0]	values[0]	values[5]	398	1			T171	12		T44	27		T162	20
auto[0]	values[0]	values[6]	377	1			T43	56		T172	8		T79	20
auto[0]	values[0]	values[7]	241	1			T173	20		T174	4		T175	20
auto[0]	values[1]	values[0]	589	1			T4	12		T47	25		T166	19
auto[0]	values[1]	values[1]	386	1			T79	27		T176	22		T177	93
auto[0]	values[1]	values[2]	471	1			T36	18		T42	22		T47	30
auto[0]	values[1]	values[3]	351	1			T24	29		T178	16		T38	49
auto[0]	values[1]	values[4]	315	1			T167	27		T179	14		T180	4
auto[0]	values[1]	values[5]	264	1			T36	101		T167	20		T45	20
auto[0]	values[1]	values[6]	389	1			T44	21		T45	22		T166	27
auto[0]	values[1]	values[7]	378	1			T12	20		T181	22		T182	12
auto[0]	values[2]	values[0]	228	1			T183	14		T184	35		T185	26
auto[0]	values[2]	values[1]	359	1			T42	19		T186	20		T177	20
auto[0]	values[2]	values[2]	264	1			T36	20		T43	62		T173	20
auto[0]	values[2]	values[3]	374	1			T38	40		T187	31		T188	20
auto[0]	values[2]	values[4]	399	1			T35	10		T36	87		T189	2
auto[0]	values[2]	values[5]	480	1			T91	22		T46	18		T190	23
auto[0]	values[2]	values[6]	413	1			T39	6		T40	12		T36	100
auto[0]	values[2]	values[7]	144	1			T9	4		T191	8		T192	20
auto[0]	values[3]	values[0]	525	1			T38	29		T43	20		T175	20
auto[0]	values[3]	values[1]	502	1			T193	16		T184	19		T194	151
auto[0]	values[3]	values[2]	274	1			T157	2		T195	4		T79	20
auto[0]	values[3]	values[3]	542	1			T47	27		T173	19		T196	10
auto[0]	values[3]	values[4]	295	1			T167	19		T197	14		T198	2
auto[0]	values[3]	values[5]	366	1			T156	22		T34	20		T190	44
auto[0]	values[3]	values[6]	454	1			T199	16		T177	42		T200	53
auto[0]	values[3]	values[7]	185	1			T34	20		T38	30		T80	20
auto[0]	values[4]	values[0]	574	1			T38	20		T162	20		T173	22
auto[0]	values[4]	values[1]	261	1			T38	18		T79	20		T201	4
auto[0]	values[4]	values[2]	290	1			T41	14		T43	53		T202	12
auto[0]	values[4]	values[3]	508	1			T24	75		T166	20		T177	24
auto[0]	values[4]	values[4]	348	1			T203	47		T46	19		T192	20
auto[0]	values[4]	values[5]	523	1			T43	20		T190	20		T184	19
auto[0]	values[4]	values[6]	465	1			T13	8		T99	4		T204	4
auto[0]	values[4]	values[7]	349	1			T24	25		T47	34		T188	20
auto[0]	values[5]	values[0]	340	1			T24	43		T205	4		T38	18
auto[0]	values[5]	values[1]	489	1			T34	23		T42	20		T206	6
auto[0]	values[5]	values[2]	339	1			T207	2		T208	28		T45	22
auto[0]	values[5]	values[3]	516	1			T11	6		T31	12		T38	20
auto[0]	values[5]	values[4]	369	1			T36	20		T209	18		T44	20
auto[0]	values[5]	values[5]	291	1			T210	14		T211	27		T200	21
auto[0]	values[5]	values[6]	326	1			T43	20		T44	20		T47	33
auto[0]	values[5]	values[7]	352	1			T36	42		T212	20		T80	20
auto[0]	values[6]	values[0]	257	1			T6	20		T188	22		T177	27
auto[0]	values[6]	values[1]	287	1			T43	20		T213	10		T169	27
auto[0]	values[6]	values[2]	271	1			T45	33		T166	20		T175	27
auto[0]	values[6]	values[3]	382	1			T214	10		T44	20		T47	20
auto[0]	values[6]	values[4]	389	1			T36	25		T212	20		T188	20
auto[0]	values[6]	values[5]	238	1			T154	16		T43	20		T215	4
auto[0]	values[6]	values[6]	310	1			T190	39		T185	20		T216	18
auto[0]	values[6]	values[7]	337	1			T47	19		T194	21		T188	21
auto[0]	values[7]	values[0]	348	1			T36	19		T45	20		T217	2
auto[0]	values[7]	values[1]	244	1			T5	2		T44	26		T218	10
auto[0]	values[7]	values[2]	503	1			T219	10		T186	26		T47	23
auto[0]	values[7]	values[3]	258	1			T155	10		T38	20		T173	24
auto[0]	values[7]	values[4]	281	1			T44	20		T220	2		T221	18
auto[0]	values[7]	values[5]	716	1			T33	16		T24	40		T42	117
auto[0]	values[7]	values[6]	328	1			T42	20		T222	4		T185	77
auto[0]	values[7]	values[7]	502	1			T34	18		T45	33		T162	23
auto[1]	values[0]	values[0]	9	1			T53	1		T25	2		T123	3
auto[1]	values[0]	values[1]	7	1			T47	2		T166	3		T185	1
auto[1]	values[0]	values[2]	5	1			T42	1		T88	1		T223	1
auto[1]	values[0]	values[3]	8	1			T168	2		T169	1		T224	2
auto[1]	values[0]	values[4]	7	1			T211	1		T225	1		T226	2
auto[1]	values[0]	values[5]	1	1			T53	1		-	-		-	-
auto[1]	values[0]	values[6]	13	1			T88	5		T227	1		T151	1
auto[1]	values[1]	values[0]	9	1			T166	1		T184	1		T187	1
auto[1]	values[1]	values[1]	13	1			T177	1		T200	1		T25	3
auto[1]	values[1]	values[2]	8	1			T36	2		T47	1		T88	3
auto[1]	values[1]	values[3]	4	1			T228	2		T229	1		T230	1
auto[1]	values[1]	values[4]	11	1			T167	1		T169	4		T231	1
auto[1]	values[1]	values[5]	3	1			T232	1		T233	2		-	-
auto[1]	values[1]	values[6]	12	1			T44	1		T45	1		T234	4
auto[1]	values[1]	values[7]	6	1			T235	1		T151	1		T152	2
auto[1]	values[2]	values[0]	2	1			T236	2		-	-		-	-
auto[1]	values[2]	values[1]	8	1			T42	1		T227	1		T237	1
auto[1]	values[2]	values[3]	7	1			T38	3		T188	1		T175	1
auto[1]	values[2]	values[4]	7	1			T36	2		T80	1		T228	1
auto[1]	values[2]	values[5]	10	1			T46	2		T175	2		T238	1
auto[1]	values[2]	values[6]	7	1			T36	1		T236	2		T226	4
auto[1]	values[2]	values[7]	3	1			T188	1		T226	1		T151	1
auto[1]	values[3]	values[0]	15	1			T38	5		T239	2		T240	3
auto[1]	values[3]	values[1]	3	1			T184	1		T241	2		-	-
auto[1]	values[3]	values[2]	3	1			T45	2		T235	1		-	-
auto[1]	values[3]	values[3]	12	1			T47	2		T173	1		T242	6
auto[1]	values[3]	values[4]	15	1			T167	1		T197	6		T243	4
auto[1]	values[3]	values[5]	10	1			T244	2		T231	2		T245	2
auto[1]	values[3]	values[6]	7	1			T200	1		T236	2		T246	1
auto[1]	values[3]	values[7]	4	1			T80	1		T235	3		-	-
auto[1]	values[4]	values[0]	3	1			T247	1		T228	1		T248	1
auto[1]	values[4]	values[1]	7	1			T38	2		T239	1		T235	3
auto[1]	values[4]	values[3]	3	1			T249	1		T250	2		-	-
auto[1]	values[4]	values[4]	2	1			T46	1		T251	1		-	-
auto[1]	values[4]	values[5]	17	1			T184	1		T192	3		T239	1
auto[1]	values[4]	values[6]	13	1			T47	2		T190	1		T88	2
auto[1]	values[4]	values[7]	5	1			T24	1		T150	1		T88	1
auto[1]	values[5]	values[0]	6	1			T38	2		T224	2		T250	2
auto[1]	values[5]	values[1]	7	1			T34	1		T234	1		T55	1
auto[1]	values[5]	values[2]	7	1			T200	1		T238	2		T228	2
auto[1]	values[5]	values[3]	17	1			T31	4		T43	3		T53	3
auto[1]	values[5]	values[4]	7	1			T80	1		T175	3		T232	1
auto[1]	values[5]	values[5]	5	1			T200	1		T88	3		T230	1
auto[1]	values[5]	values[6]	3	1			T192	1		T240	1		T124	1
auto[1]	values[5]	values[7]	5	1			T55	1		T88	4		-	-
auto[1]	values[6]	values[0]	8	1			T252	2		T253	1		T249	2
auto[1]	values[6]	values[1]	3	1			T169	1		T223	1		T254	1
auto[1]	values[6]	values[2]	4	1			T45	1		T255	2		T251	1
auto[1]	values[6]	values[3]	7	1			T185	1		T177	3		T238	1
auto[1]	values[6]	values[4]	11	1			T256	2		T25	4		T257	2
auto[1]	values[6]	values[5]	2	1			T258	2		-	-		-	-
auto[1]	values[6]	values[6]	4	1			T216	2		T169	1		T88	1
auto[1]	values[6]	values[7]	7	1			T47	1		T194	1		T188	2
auto[1]	values[7]	values[0]	9	1			T36	1		T25	2		T252	4
auto[1]	values[7]	values[1]	1	1			T259	1		-	-		-	-
auto[1]	values[7]	values[2]	7	1			T190	4		T173	1		T53	2
auto[1]	values[7]	values[3]	1	1			T173	1		-	-		-	-
auto[1]	values[7]	values[4]	8	1			T80	4		T260	2		T152	2
auto[1]	values[7]	values[5]	6	1			T42	3		T261	2		T234	1
auto[1]	values[7]	values[6]	7	1			T185	2		T211	1		T262	1
auto[1]	values[7]	values[7]	13	1			T34	2		T45	2		T190	1