Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1948

1

T7

3

T15

14

T17

7

auto[1]

1951

1

T15

12

T17

7

T18

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2093

1

T7

3

T15

26

T19

2

auto[1]

1806

1

T17

14

T18

3

T19

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3086

1

T15

17

T17

14

T18

3

auto[1]

813

1

T7

3

T15

9

T19

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	743	1			T15	5		T17	1		T20	1
valid[1]	805	1			T15	6		T17	1		T19	1
valid[2]	768	1			T7	1		T15	7		T17	4
valid[3]	800	1			T7	1		T15	1		T17	5
valid[4]	783	1			T7	1		T15	7		T17	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	131	1			T15	2		T28	1		T30	1
auto[0]	auto[0]	valid[0]	auto[1]	164	1			T22	1		T29	1		T52	1
auto[0]	auto[0]	valid[1]	auto[0]	134	1			T15	3		T38	1		T334	1
auto[0]	auto[0]	valid[1]	auto[1]	180	1			T20	1		T52	1		T342	2
auto[0]	auto[0]	valid[2]	auto[0]	116	1			T15	2		T28	1		T333	1
auto[0]	auto[0]	valid[2]	auto[1]	170	1			T17	2		T22	2		T29	1
auto[0]	auto[0]	valid[3]	auto[0]	135	1			T29	2		T51	2		T38	1
auto[0]	auto[0]	valid[3]	auto[1]	205	1			T17	4		T19	1		T22	3
auto[0]	auto[0]	valid[4]	auto[0]	139	1			T15	3		T19	1		T28	2
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T17	1		T52	6		T333	1
auto[0]	auto[1]	valid[0]	auto[0]	123	1			T15	2		T20	1		T22	1
auto[0]	auto[1]	valid[0]	auto[1]	173	1			T17	1		T52	5		T333	1
auto[0]	auto[1]	valid[1]	auto[0]	126	1			T15	2		T22	1		T28	1
auto[0]	auto[1]	valid[1]	auto[1]	190	1			T17	1		T52	6		T333	1
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T15	2		T22	2		T30	1
auto[0]	auto[1]	valid[2]	auto[1]	203	1			T17	2		T18	1		T52	6
auto[0]	auto[1]	valid[3]	auto[0]	126	1			T15	1		T28	2		T29	1
auto[0]	auto[1]	valid[3]	auto[1]	163	1			T17	1		T18	2		T19	1
auto[0]	auto[1]	valid[4]	auto[0]	130	1			T22	2		T29	1		T30	1
auto[0]	auto[1]	valid[4]	auto[1]	193	1			T17	2		T19	2		T22	2
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T22	1		T28	1		T30	1
auto[1]	auto[0]	valid[1]	auto[0]	75	1			T15	1		T30	1		T334	1
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T7	1		T15	1		T22	1
auto[1]	auto[0]	valid[3]	auto[0]	94	1			T7	1		T22	1		T30	2
auto[1]	auto[0]	valid[4]	auto[0]	84	1			T7	1		T15	2		T22	1
auto[1]	auto[1]	valid[0]	auto[0]	73	1			T15	1		T22	1		T333	2
auto[1]	auto[1]	valid[1]	auto[0]	100	1			T19	1		T28	1		T29	4
auto[1]	auto[1]	valid[2]	auto[0]	82	1			T15	2		T22	1		T89	2
auto[1]	auto[1]	valid[3]	auto[0]	77	1			T20	1		T22	1		T30	1
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T15	2		T51	1		T265	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal