Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53668

1

T7

13

T15

506

T19

219

auto[1]

19153

1

T17

14

T18

3

T19

56

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52904

1

T7

6

T15

339

T17

14

auto[1]

19917

1

T7

7

T15

167

T19

77

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	37289	1			T7	5		T15	238		T17	14
others[1]	6287	1			T7	3		T15	45		T19	25
others[2]	6005	1			T15	56		T19	25		T20	9
others[3]	7051	1			T7	1		T15	48		T19	29
interest[1]	4001	1			T7	2		T15	25		T19	8
interest[4]	24516	1			T7	4		T15	152		T17	14
interest[64]	12188	1			T7	2		T15	94		T19	46

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17244	1			T7	1		T15	154		T19	73
auto[0]	auto[0]	others[1]	2982	1			T7	3		T15	32		T19	13
auto[0]	auto[0]	others[2]	2761	1			T15	37		T19	17		T20	5
auto[0]	auto[0]	others[3]	3220	1			T15	37		T19	15		T20	3
auto[0]	auto[0]	interest[1]	1843	1			T7	1		T15	16		T19	4
auto[0]	auto[0]	interest[4]	11322	1			T7	1		T15	104		T19	45
auto[0]	auto[0]	interest[64]	5701	1			T7	1		T15	63		T19	20
auto[0]	auto[1]	others[0]	9892	1			T17	14		T18	3		T19	32
auto[0]	auto[1]	others[1]	1578	1			T19	4		T20	2		T22	7
auto[0]	auto[1]	others[2]	1599	1			T19	2		T20	1		T22	7
auto[0]	auto[1]	others[3]	1890	1			T19	8		T22	13		T29	4
auto[0]	auto[1]	interest[1]	1052	1			T19	1		T20	1		T22	4
auto[0]	auto[1]	interest[4]	6553	1			T17	14		T18	3		T19	20
auto[0]	auto[1]	interest[64]	3142	1			T19	9		T20	2		T22	18
auto[1]	auto[0]	others[0]	10153	1			T7	4		T15	84		T19	37
auto[1]	auto[0]	others[1]	1727	1			T15	13		T19	8		T20	3
auto[1]	auto[0]	others[2]	1645	1			T15	19		T19	6		T20	3
auto[1]	auto[0]	others[3]	1941	1			T7	1		T15	11		T19	6
auto[1]	auto[0]	interest[1]	1106	1			T7	1		T15	9		T19	3
auto[1]	auto[0]	interest[4]	6641	1			T7	3		T15	48		T19	23
auto[1]	auto[0]	interest[64]	3345	1			T7	1		T15	31		T19	17

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal