Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	771	1			T30	7		T42	20		T44	4
all_values[1]	771	1			T30	7		T42	20		T44	4
all_values[2]	771	1			T30	7		T42	20		T44	4
all_values[3]	771	1			T30	7		T42	20		T44	4
all_values[4]	771	1			T30	7		T42	20		T44	4
all_values[5]	771	1			T30	7		T42	20		T44	4
all_values[6]	771	1			T30	7		T42	20		T44	4
all_values[7]	771	1			T30	7		T42	20		T44	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3278

1

T30

24

T42

90

T44

22

auto[1]

2890

1

T30

32

T42

70

T44

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425

1

T30

25

T42

67

T44

14

auto[1]

3743

1

T30

31

T42

93

T44

18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3555

1

T30

36

T42

101

T44

19

auto[1]

2613

1

T30

20

T42

59

T44

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	135	1			T42	6		T44	2		T72	3
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T42	2		T72	1		T162	1
all_values[0]	auto[0]	auto[1]	auto[0]	134	1			T42	4		T44	2		T72	3
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T30	5		T42	2		T73	3
all_values[0]	auto[1]	auto[0]	auto[1]	190	1			T30	1		T42	4		T72	4
all_values[0]	auto[1]	auto[1]	auto[1]	146	1			T30	1		T42	2		T72	3
all_values[1]	auto[0]	auto[0]	auto[0]	162	1			T30	4		T42	5		T44	2
all_values[1]	auto[0]	auto[0]	auto[1]	79	1			T30	1		T42	4		T72	1
all_values[1]	auto[0]	auto[1]	auto[0]	122	1			T42	3		T72	4		T73	2
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T42	1		T72	1		T73	3
all_values[1]	auto[1]	auto[0]	auto[1]	161	1			T30	2		T42	6		T44	2
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T42	1		T72	2		T73	2
all_values[2]	auto[0]	auto[0]	auto[0]	155	1			T42	9		T44	1		T72	1
all_values[2]	auto[0]	auto[0]	auto[1]	85	1			T30	1		T72	3		T73	2
all_values[2]	auto[0]	auto[1]	auto[0]	127	1			T42	4		T72	1		T73	2
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T30	1		T42	2		T44	1
all_values[2]	auto[1]	auto[0]	auto[1]	191	1			T30	3		T42	2		T44	2
all_values[2]	auto[1]	auto[1]	auto[1]	139	1			T30	2		T42	3		T72	5
all_values[3]	auto[0]	auto[0]	auto[0]	135	1			T30	4		T42	3		T72	1
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T42	4		T72	3		T73	2
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T42	4		T73	2		T162	3
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T30	1		T42	4		T44	2
all_values[3]	auto[1]	auto[0]	auto[1]	194	1			T30	1		T42	3		T44	1
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T30	1		T42	2		T44	1
all_values[4]	auto[0]	auto[0]	auto[0]	161	1			T42	2		T44	1		T72	4
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T42	2		T44	1		T72	4
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T30	7		T42	3		T72	1
all_values[4]	auto[0]	auto[1]	auto[1]	92	1			T42	3		T73	1		T162	2
all_values[4]	auto[1]	auto[0]	auto[1]	157	1			T42	3		T44	2		T72	4
all_values[4]	auto[1]	auto[1]	auto[1]	159	1			T42	7		T72	1		T73	3
all_values[5]	auto[0]	auto[0]	auto[0]	223	1			T42	7		T72	4		T73	3
all_values[5]	auto[0]	auto[1]	auto[0]	227	1			T30	4		T42	8		T44	1
all_values[5]	auto[1]	auto[0]	auto[1]	163	1			T42	3		T44	1		T72	4
all_values[5]	auto[1]	auto[1]	auto[1]	158	1			T30	3		T42	2		T44	2
all_values[6]	auto[0]	auto[0]	auto[0]	172	1			T30	3		T42	3		T44	3
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T30	1		T42	3		T72	2
all_values[6]	auto[0]	auto[1]	auto[0]	107	1			T42	1		T72	1		T73	3
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T42	1		T72	1		T162	3
all_values[6]	auto[1]	auto[0]	auto[1]	174	1			T30	1		T42	6		T44	1
all_values[6]	auto[1]	auto[1]	auto[1]	156	1			T30	2		T42	6		T72	1
all_values[7]	auto[0]	auto[0]	auto[0]	152	1			T42	3		T44	1		T72	2
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T30	1		T42	5		T44	1
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T30	3		T42	2		T44	1
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T42	1		T72	1		T73	1
all_values[7]	auto[1]	auto[0]	auto[1]	186	1			T30	1		T42	5		T44	1
all_values[7]	auto[1]	auto[1]	auto[1]	142	1			T30	2		T42	4		T72	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal