Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2582277	1			T1	1		T2	8251		T3	3563
all_values[1]	2582277	1			T1	1		T2	8251		T3	3563
all_values[2]	2582277	1			T1	1		T2	8251		T3	3563
all_values[3]	2582277	1			T1	1		T2	8251		T3	3563
all_values[4]	2582277	1			T1	1		T2	8251		T3	3563
all_values[5]	2582277	1			T1	1		T2	8251		T3	3563
all_values[6]	2582277	1			T1	1		T2	8251		T3	3563
all_values[7]	2582277	1			T1	1		T2	8251		T3	3563

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20296124

1

T1

8

T2

65972

T3

28504

auto[1]

362092

1

T2

36

T53

33

T57

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20636484

1

T1

8

T2

65662

T3

28500

auto[1]

21732

1

T2

346

T3

4

T5

135

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2545379	1			T1	1		T2	8051		T3	3563
all_values[0]	auto[0]	auto[1]	11378	1			T2	193		T5	97		T9	44
all_values[0]	auto[1]	auto[0]	25096	1			T2	7		T53	2		T57	2
all_values[0]	auto[1]	auto[1]	424	1			T57	2		T29	1		T58	1
all_values[1]	auto[0]	auto[0]	2562586	1			T1	1		T2	8138		T3	3563
all_values[1]	auto[0]	auto[1]	5285	1			T2	112		T5	26		T10	16
all_values[1]	auto[1]	auto[0]	14148	1			T53	5		T59	4		T29	1
all_values[1]	auto[1]	auto[1]	258	1			T2	1		T53	2		T57	2
all_values[2]	auto[0]	auto[0]	2515578	1			T1	1		T2	8228		T3	3563
all_values[2]	auto[0]	auto[1]	2316	1			T2	17		T5	12		T23	17
all_values[2]	auto[1]	auto[0]	64156	1			T2	3		T53	4		T57	1
all_values[2]	auto[1]	auto[1]	227	1			T2	3		T57	2		T59	2
all_values[3]	auto[0]	auto[0]	2507816	1			T1	1		T2	8248		T3	3563
all_values[3]	auto[0]	auto[1]	164	1			T2	2		T53	1		T57	2
all_values[3]	auto[1]	auto[0]	74121	1			T2	1		T53	6		T57	2
all_values[3]	auto[1]	auto[1]	176	1			T57	2		T29	2		T58	3
all_values[4]	auto[0]	auto[0]	2516300	1			T1	1		T2	8245		T3	3563
all_values[4]	auto[0]	auto[1]	147	1			T2	1		T53	1		T57	1
all_values[4]	auto[1]	auto[0]	65628	1			T2	1		T53	1		T57	4
all_values[4]	auto[1]	auto[1]	202	1			T2	4		T53	1		T57	3
all_values[5]	auto[0]	auto[0]	2513768	1			T1	1		T2	8245		T3	3559
all_values[5]	auto[0]	auto[1]	283	1			T3	4		T7	3		T170	3
all_values[5]	auto[1]	auto[0]	68069	1			T2	2		T53	2		T57	4
all_values[5]	auto[1]	auto[1]	157	1			T2	4		T57	2		T59	2
all_values[6]	auto[0]	auto[0]	2538188	1			T1	1		T2	8244		T3	3563
all_values[6]	auto[0]	auto[1]	185	1			T2	3		T58	4		T32	4
all_values[6]	auto[1]	auto[0]	43716	1			T53	1		T57	5		T59	4
all_values[6]	auto[1]	auto[1]	188	1			T2	4		T53	2		T57	1
all_values[7]	auto[0]	auto[0]	2576570	1			T1	1		T2	8244		T3	3563
all_values[7]	auto[0]	auto[1]	181	1			T2	1		T57	4		T59	3
all_values[7]	auto[1]	auto[0]	5365	1			T2	5		T53	7		T57	4
all_values[7]	auto[1]	auto[1]	161	1			T2	1		T58	3		T32	5