Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	30567	1			T1	4		T2	161		T4	8
auto[SpiFlashAddrCfg]	6531	1			T2	56		T4	8		T5	24
auto[SpiFlashAddr3b]	7731	1			T1	2		T2	46		T5	17
auto[SpiFlashAddr4b]	6521	1			T1	2		T2	35		T4	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28173

1

T1

8

T2

164

T5

66

auto[1]

23177

1

T2

134

T4

18

T5

48

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27475

1

T1

8

T2

166

T4

16

auto[1]

23875

1

T2

132

T4

2

T5

44

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34576	1			T1	6		T2	183		T4	10
values[1]	953	1			T2	8		T5	5		T9	5
values[2]	1294	1			T1	2		T2	5		T4	6
values[3]	1287	1			T2	6		T5	3		T9	2
values[4]	1270	1			T2	8		T5	3		T9	5
values[5]	1262	1			T2	9		T5	4		T10	6
values[6]	1245	1			T2	3		T5	6		T10	6
values[7]	1261	1			T2	8		T5	2		T9	2
values[8]	8202	1			T2	68		T4	2		T5	26

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25869

1

T1

8

T4

18

T5

114

auto[1]

25481

1

T2

298

T9

45

T10

458

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

49551

1

T1

8

T2

286

T4

18

write

1799

1

T2

12

T5

6

T9

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16986

1

T2

116

T4

8

T5

51

valids[0x1]

34364

1

T1

8

T2

182

T4

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1475	1			T2	6		T4	2		T5	4
internal_process_ops[0x5a]	1292	1			T2	7		T5	4		T9	4
internal_process_ops[0x05]	18388	1			T1	2		T2	64		T4	4
internal_process_ops[0x35]	1376	1			T1	2		T2	11		T4	2
internal_process_ops[0x15]	1438	1			T2	12		T5	8		T10	16
internal_process_ops[0x03]	898	1			T2	5		T5	1		T9	1
internal_process_ops[0x0b]	900	1			T2	4		T5	4		T9	1
internal_process_ops[0x3b]	870	1			T2	2		T5	4		T9	1
internal_process_ops[0x6b]	880	1			T2	2		T5	4		T9	1
internal_process_ops[0xbb]	887	1			T2	4		T4	6		T5	2
internal_process_ops[0xeb]	914	1			T2	1		T5	4		T9	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50466

1

T1

8

T2

292

T4

18

auto[1]

884

1

T2

6

T5

4

T9

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49585

1

T1

8

T2

286

T4

18

auto[1]

1765

1

T2

12

T5

8

T9

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7912

1

T1

4

T5

36

T11

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6264

1

T4

8

T5

17

T20

60

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1871

1

T5

12

T12

2

T14

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1522

1

T4

8

T5

11

T20

20

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2108

1

T1

2

T5

6

T11

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1861

1

T5

10

T20

33

T24

38

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1871

1

T1

2

T5

10

T11

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1597

1

T4

2

T5

6

T20

15

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

52

1

T24

2

T162

2

T17

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

42

1

T27

2

T57

1

T28

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

59

1

T20

1

T24

6

T57

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

58

1

T5

1

T24

1

T57

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

53

1

T138

2

T24

1

T163

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

63

1

T5

1

T24

3

T27

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

37

1

T24

1

T164

3

T29

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

59

1

T20

2

T24

1

T57

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

66

1

T11

2

T24

1

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

50

1

T24

1

T27

1

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

55

1

T5

1

T24

1

T165

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

70

1

T24

1

T28

1

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

59

1

T5

1

T24

1

T166

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

48

1

T20

2

T27

2

T164

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

40

1

T165

2

T167

1

T168

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

52

1

T5

2

T20

1

T28

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9124

1

T2

101

T9

15

T10

138

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6839

1

T2

53

T9

10

T10

166

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1355

1

T2

23

T9

7

T10

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1320

1

T2

31

T9

3

T10

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1706

1

T2

17

T9

4

T10

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1579

1

T2

29

T9

3

T10

26

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1296

1

T2

16

T9

1

T10

21

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1326

1

T2

16

T9

1

T10

28

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

68

1

T2

3

T23

2

T57

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

57

1

T2

3

T21

1

T23

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

41

1

T2

1

T10

1

T23

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

51

1

T10

1

T21

2

T23

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

74

1

T21

2

T33

1

T75

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

50

1

T9

1

T10

3

T21

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

69

1

T10

1

T21

1

T33

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

58

1

T2

2

T21

4

T23

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

70

1

T21

2

T33

2

T57

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

59

1

T23

5

T33

2

T57

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

53

1

T10

2

T33

1

T57

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

54

1

T10

1

T21

1

T33

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

55

1

T2

1

T10

1

T23

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

64

1

T10

3

T33

3

T169

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

64

1

T2

1

T10

1

T23

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

49

1

T2

1

T23

1

T75

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3511	1			T5	21		T14	2		T26	4
auto[0]	values[0]	valids[0x1]	13055	1			T1	6		T4	10		T5	42
auto[0]	values[1]	valids[0x1]	447	1			T5	5		T11	2		T20	3
auto[0]	values[2]	valids[0x0]	460	1			T4	6		T5	1		T20	8
auto[0]	values[2]	valids[0x1]	253	1			T1	2		T5	1		T25	4
auto[0]	values[3]	valids[0x0]	440	1			T5	1		T20	8		T24	5
auto[0]	values[3]	valids[0x1]	291	1			T5	2		T11	4		T20	3
auto[0]	values[4]	valids[0x0]	453	1			T5	1		T87	2		T20	8
auto[0]	values[4]	valids[0x1]	239	1			T5	2		T12	2		T87	2
auto[0]	values[5]	valids[0x0]	450	1			T5	2		T11	4		T20	4
auto[0]	values[5]	valids[0x1]	236	1			T5	2		T20	2		T138	2
auto[0]	values[6]	valids[0x0]	432	1			T5	4		T12	2		T20	7
auto[0]	values[6]	valids[0x1]	241	1			T5	2		T20	2		T100	2
auto[0]	values[7]	valids[0x0]	505	1			T5	2		T20	10		T24	11
auto[0]	values[7]	valids[0x1]	232	1			T12	4		T20	3		T24	1
auto[0]	values[8]	valids[0x0]	2915	1			T4	2		T5	19		T11	2
auto[0]	values[8]	valids[0x1]	1709	1			T5	7		T12	4		T14	2
auto[1]	values[0]	valids[0x0]	3700	1			T2	58		T9	9		T10	71
auto[1]	values[0]	valids[0x1]	14310	1			T2	125		T9	12		T10	261
auto[1]	values[1]	valids[0x1]	506	1			T2	8		T9	5		T10	7
auto[1]	values[2]	valids[0x0]	346	1			T2	3		T9	1		T10	7
auto[1]	values[2]	valids[0x1]	235	1			T2	2		T21	1		T23	1
auto[1]	values[3]	valids[0x0]	308	1			T2	3		T10	5		T21	3
auto[1]	values[3]	valids[0x1]	248	1			T2	3		T9	2		T10	1
auto[1]	values[4]	valids[0x0]	347	1			T2	6		T9	3		T10	10
auto[1]	values[4]	valids[0x1]	231	1			T2	2		T9	2		T10	4
auto[1]	values[5]	valids[0x0]	342	1			T2	3		T10	5		T21	3
auto[1]	values[5]	valids[0x1]	234	1			T2	6		T10	1		T21	2
auto[1]	values[6]	valids[0x0]	346	1			T21	10		T23	4		T33	7
auto[1]	values[6]	valids[0x1]	226	1			T2	3		T10	6		T21	2
auto[1]	values[7]	valids[0x0]	310	1			T2	4		T9	1		T10	9
auto[1]	values[7]	valids[0x1]	214	1			T2	4		T9	1		T10	1
auto[1]	values[8]	valids[0x0]	2121	1			T2	39		T9	4		T10	36
auto[1]	values[8]	valids[0x1]	1457	1			T2	29		T9	5		T10	34