Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3160344

1

T1

1

T2

17032

T4

1

auto[1]

17032

1

T2

58

T5

14

T9

5

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057379

1

T1

1

T2

64

T4

1

auto[1]

2119997

1

T2

17026

T5

14632

T9

1827

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	621778	1			T1	1		T2	2353		T4	1
auto[524288:1048575]	374559	1			T2	2904		T5	519		T9	801
auto[1048576:1572863]	332028	1			T2	785		T5	514		T10	8811
auto[1572864:2097151]	369171	1			T2	3112		T9	513		T10	4453
auto[2097152:2621439]	419864	1			T2	543		T5	2986		T10	1
auto[2621440:3145727]	322908	1			T2	2243		T5	4		T9	5
auto[3145728:3670015]	366435	1			T2	2043		T5	138		T10	790
auto[3670016:4194303]	370633	1			T2	3107		T5	8042		T10	1338

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2139384

1

T1

1

T2

17089

T4

1

auto[1]

1037992

1

T2

1

T10

2

T13

35658

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2779729

1

T1

1

T2

11206

T4

1

auto[1]

397647

1

T2

5884

T5

10510

T9

5

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	222327	1			T1	1		T2	3		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	339501	1			T2	1		T5	513		T9	513
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	96112	1			T2	10		T5	3		T9	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	214208	1			T2	386		T5	513		T9	798
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	111380	1			T2	6		T5	2		T10	14
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	167156	1			T2	1		T5	256		T10	8501
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	122010	1			T2	2		T9	1		T10	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	210352	1			T2	2849		T9	512		T10	3790
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	179849	1			T2	6		T5	8		T10	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	187923	1			T2	516		T5	2715		T21	734
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	91998	1			T2	8		T5	2		T10	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	186068	1			T2	2222		T5	2		T10	896
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	109048	1			T2	3		T5	4		T10	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	207969	1			T2	2040		T5	132		T21	1045
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	114811	1			T2	6		T5	1		T10	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	205411	1			T2	3090		T5	1		T10	261
auto[0]	auto[1]	auto[0:524287]	auto[0]	418	1			T5	2		T10	6		T21	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	57082	1			T2	2346		T5	1953		T10	2
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1201	1			T2	1		T5	1		T10	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	60800	1			T2	2502		T10	332		T21	258
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1885	1			T10	1		T21	7		T23	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49371	1			T2	768		T5	256		T10	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	258	1			T2	3		T10	4		T33	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	34703	1			T2	258		T10	600		T33	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1316	1			T2	1		T5	3		T23	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48643	1			T5	257		T23	932		T33	519
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	876	1			T2	3		T9	2		T21	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	41974	1			T2	1		T9	1		T21	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	922	1			T10	8		T23	4		T20	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	46456	1			T10	780		T21	256		T23	257
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1200	1			T5	6		T10	6		T21	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	47116	1			T5	8028		T10	1031		T24	774
auto[1]	auto[0]	auto[0:524287]	auto[0]	202	1			T2	1		T5	1		T9	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1680	1			T2	2		T9	2		T10	39
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	191	1			T2	2		T5	1		T10	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1671	1			T2	3		T5	1		T10	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	175	1			T2	1		T10	7		T33	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1555	1			T2	9		T10	32		T33	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	147	1			T10	5		T23	1		T33	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1373	1			T10	45		T23	1		T33	43
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	159	1			T2	4		T5	2		T21	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1640	1			T2	16		T21	1		T20	11
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	190	1			T2	1		T21	1		T23	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1359	1			T2	7		T21	10		T24	19
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	181	1			T5	1		T21	1		T20	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1440	1			T5	1		T21	1		T20	9
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	159	1			T2	2		T5	1		T10	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1484	1			T2	9		T5	2		T10	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	57	1			T10	2		T33	1		T57	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	511	1			T10	6		T33	27		T28	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	50	1			T10	1		T20	1		T33	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	326	1			T33	10		T24	1		T169	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	50	1			T21	1		T28	4		T223	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	456	1			T21	1		T28	41		T223	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	38	1			T75	1		T169	1		T17	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	290	1			T75	1		T169	22		T224	50
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	36	1			T5	1		T23	1		T33	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	298	1			T23	1		T33	10		T150	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	56	1			T2	1		T9	1		T21	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	387	1			T9	1		T21	16		T23	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	39	1			T23	1		T192	1		T164	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	380	1			T23	4		T192	26		T164	41
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	38	1			T5	1		T10	2		T24	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	414	1			T5	2		T10	33		T57	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1734360	1			T1	1		T2	11149		T4	1
auto[0]	auto[0]	auto[1]	1031763	1			T10	1		T13	35658		T26	206
auto[0]	auto[1]	auto[0]	388328	1			T2	5883		T5	10506		T9	3
auto[0]	auto[1]	auto[1]	5893	1			T10	1		T21	1		T33	1
auto[1]	auto[0]	auto[0]	13343	1			T2	56		T5	10		T9	3
auto[1]	auto[0]	auto[1]	263	1			T2	1		T21	1		T20	2
auto[1]	auto[1]	auto[0]	3353	1			T2	1		T5	4		T9	2
auto[1]	auto[1]	auto[1]	73	1			T21	1		T33	1		T169	1