Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14195

1

T1

8

T5

66

T11

18

auto[1]

11674

1

T4

18

T5

48

T20

132

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2693	1			T5	24		T100	4		T24	85
values[1]	2861	1			T5	47		T12	26		T13	18
values[2]	3164	1			T1	8		T20	43		T24	87
values[3]	3510	1			T5	21		T11	18		T14	14
values[4]	3571	1			T26	4		T20	105		T24	20
values[5]	3628	1			T20	22		T137	16		T24	20
values[6]	2895	1			T20	20		T102	10		T207	16
values[7]	3547	1			T4	18		T5	22		T20	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3451	1			T5	20		T24	41		T27	24
values[1]	2265	1			T1	8		T87	8		T20	20
values[2]	3390	1			T12	26		T20	21		T24	64
values[3]	3250	1			T5	24		T14	14		T25	8
values[4]	2938	1			T5	22		T24	23		T244	16
values[5]	3603	1			T5	21		T13	18		T26	4
values[6]	3193	1			T4	18		T5	27		T20	42
values[7]	3779	1			T11	18		T86	2		T20	48

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	152	1			T29	19		T17	16		T19	15
auto[0]	values[0]	values[1]	227	1			T24	8		T27	61		T163	15
auto[0]	values[0]	values[2]	251	1			T24	8		T226	22		T150	12
auto[0]	values[0]	values[3]	208	1			T5	15		T100	4		T189	10
auto[0]	values[0]	values[4]	76	1			T30	10		T245	6		T187	13
auto[0]	values[0]	values[5]	249	1			T24	17		T246	12		T84	10
auto[0]	values[0]	values[6]	234	1			T193	67		T211	8		T229	48
auto[0]	values[0]	values[7]	165	1			T24	16		T247	6		T17	14
auto[0]	values[1]	values[0]	233	1			T5	11		T248	24		T183	24
auto[0]	values[1]	values[1]	165	1			T249	12		T167	12		T215	10
auto[0]	values[1]	values[2]	167	1			T12	26		T24	11		T27	14
auto[0]	values[1]	values[3]	262	1			T250	4		T32	39		T19	14
auto[0]	values[1]	values[4]	161	1			T24	8		T29	16		T222	12
auto[0]	values[1]	values[5]	239	1			T13	18		T138	8		T212	2
auto[0]	values[1]	values[6]	242	1			T5	19		T57	15		T28	12
auto[0]	values[1]	values[7]	246	1			T251	10		T252	16		T253	12
auto[0]	values[2]	values[0]	216	1			T24	16		T254	12		T167	29
auto[0]	values[2]	values[1]	164	1			T1	8		T20	11		T168	12
auto[0]	values[2]	values[2]	212	1			T28	9		T162	60		T218	11
auto[0]	values[2]	values[3]	314	1			T24	37		T255	8		T235	16
auto[0]	values[2]	values[4]	203	1			T163	14		T17	28		T209	12
auto[0]	values[2]	values[5]	145	1			T20	13		T237	4		T19	11
auto[0]	values[2]	values[6]	155	1			T28	14		T163	10		T211	10
auto[0]	values[2]	values[7]	251	1			T28	38		T17	16		T150	67
auto[0]	values[3]	values[0]	283	1			T163	13		T29	12		T150	7
auto[0]	values[3]	values[1]	114	1			T87	8		T208	13		T241	8
auto[0]	values[3]	values[2]	221	1			T24	21		T29	13		T167	18
auto[0]	values[3]	values[3]	198	1			T14	14		T25	8		T20	8
auto[0]	values[3]	values[4]	214	1			T244	16		T163	12		T17	12
auto[0]	values[3]	values[5]	287	1			T5	13		T27	14		T57	13
auto[0]	values[3]	values[6]	302	1			T28	38		T32	20		T168	17
auto[0]	values[3]	values[7]	359	1			T11	18		T86	2		T24	14
auto[0]	values[4]	values[0]	258	1			T24	9		T17	16		T19	12
auto[0]	values[4]	values[1]	94	1			T256	4		T257	4		T150	11
auto[0]	values[4]	values[2]	239	1			T20	9		T165	26		T258	14
auto[0]	values[4]	values[3]	331	1			T20	11		T57	11		T17	8
auto[0]	values[4]	values[4]	236	1			T259	26		T202	12		T227	43
auto[0]	values[4]	values[5]	291	1			T26	4		T20	11		T27	11
auto[0]	values[4]	values[6]	185	1			T260	22		T209	10		T214	12
auto[0]	values[4]	values[7]	250	1			T20	5		T29	8		T30	10
auto[0]	values[5]	values[0]	182	1			T27	16		T164	13		T31	15
auto[0]	values[5]	values[1]	150	1			T201	20		T17	9		T190	17
auto[0]	values[5]	values[2]	246	1			T164	9		T29	14		T167	30
auto[0]	values[5]	values[3]	333	1			T137	16		T28	30		T261	21
auto[0]	values[5]	values[4]	243	1			T164	22		T167	15		T183	29
auto[0]	values[5]	values[5]	167	1			T24	9		T27	7		T262	8
auto[0]	values[5]	values[6]	213	1			T20	12		T150	27		T263	13
auto[0]	values[5]	values[7]	329	1			T57	13		T82	18		T28	14
auto[0]	values[6]	values[0]	171	1			T207	16		T164	16		T29	8
auto[0]	values[6]	values[1]	228	1			T102	10		T264	10		T265	16
auto[0]	values[6]	values[2]	210	1			T165	11		T168	14		T19	10
auto[0]	values[6]	values[3]	67	1			T165	15		T150	15		T209	9
auto[0]	values[6]	values[4]	199	1			T29	12		T236	8		T32	13
auto[0]	values[6]	values[5]	257	1			T17	12		T165	12		T187	19
auto[0]	values[6]	values[6]	224	1			T20	13		T29	15		T266	8
auto[0]	values[6]	values[7]	322	1			T30	10		T32	15		T218	9
auto[0]	values[7]	values[0]	319	1			T167	18		T150	13		T202	13
auto[0]	values[7]	values[1]	87	1			T30	12		T116	22		T165	13
auto[0]	values[7]	values[2]	228	1			T27	15		T163	12		T167	12
auto[0]	values[7]	values[3]	174	1			T267	2		T17	15		T268	4
auto[0]	values[7]	values[4]	312	1			T5	8		T30	15		T17	10
auto[0]	values[7]	values[5]	219	1			T24	20		T218	18		T19	12
auto[0]	values[7]	values[6]	172	1			T269	2		T28	8		T163	29
auto[0]	values[7]	values[7]	344	1			T20	6		T27	16		T57	18
auto[1]	values[0]	values[0]	128	1			T29	21		T17	7		T19	6
auto[1]	values[0]	values[1]	234	1			T24	12		T27	10		T163	7
auto[1]	values[0]	values[2]	129	1			T24	12		T150	8		T183	9
auto[1]	values[0]	values[3]	74	1			T5	9		T211	10		T202	7
auto[1]	values[0]	values[4]	83	1			T30	10		T187	7		T48	5
auto[1]	values[0]	values[5]	199	1			T24	5		T165	25		T203	12
auto[1]	values[0]	values[6]	158	1			T211	12		T229	5		T270	46
auto[1]	values[0]	values[7]	126	1			T24	7		T17	9		T208	11
auto[1]	values[1]	values[0]	205	1			T5	9		T271	6		T183	16
auto[1]	values[1]	values[1]	104	1			T167	8		T215	10		T203	7
auto[1]	values[1]	values[2]	64	1			T24	9		T27	6		T29	7
auto[1]	values[1]	values[3]	147	1			T32	15		T19	7		T233	7
auto[1]	values[1]	values[4]	88	1			T24	15		T29	8		T272	16
auto[1]	values[1]	values[5]	238	1			T32	14		T165	5		T208	4
auto[1]	values[1]	values[6]	161	1			T5	8		T57	9		T28	15
auto[1]	values[1]	values[7]	139	1			T150	7		T241	12		T153	6
auto[1]	values[2]	values[0]	128	1			T24	5		T167	19		T211	19
auto[1]	values[2]	values[1]	199	1			T20	9		T168	12		T150	3
auto[1]	values[2]	values[2]	93	1			T28	11		T218	9		T273	8
auto[1]	values[2]	values[3]	308	1			T24	29		T235	4		T228	13
auto[1]	values[2]	values[4]	97	1			T163	6		T17	20		T209	8
auto[1]	values[2]	values[5]	135	1			T20	10		T274	2		T19	9
auto[1]	values[2]	values[6]	315	1			T28	6		T163	10		T211	144
auto[1]	values[2]	values[7]	229	1			T28	86		T17	8		T238	22
auto[1]	values[3]	values[0]	268	1			T163	7		T29	10		T150	65
auto[1]	values[3]	values[1]	167	1			T208	7		T241	59		T125	7
auto[1]	values[3]	values[2]	179	1			T24	3		T29	7		T167	2
auto[1]	values[3]	values[3]	139	1			T20	13		T28	8		T32	12
auto[1]	values[3]	values[4]	165	1			T163	10		T17	13		T32	6
auto[1]	values[3]	values[5]	186	1			T5	8		T27	6		T57	7
auto[1]	values[3]	values[6]	143	1			T28	6		T32	5		T168	3
auto[1]	values[3]	values[7]	285	1			T24	29		T29	9		T167	31
auto[1]	values[4]	values[0]	151	1			T24	11		T17	7		T19	8
auto[1]	values[4]	values[1]	50	1			T150	9		T228	9		T275	12
auto[1]	values[4]	values[2]	298	1			T20	12		T165	32		T208	34
auto[1]	values[4]	values[3]	236	1			T20	9		T57	9		T17	14
auto[1]	values[4]	values[4]	289	1			T202	8		T241	65		T184	9
auto[1]	values[4]	values[5]	267	1			T20	25		T27	9		T57	14
auto[1]	values[4]	values[6]	222	1			T276	22		T209	10		T214	8
auto[1]	values[4]	values[7]	174	1			T20	23		T29	13		T30	10
auto[1]	values[5]	values[0]	221	1			T27	8		T164	7		T31	107
auto[1]	values[5]	values[1]	107	1			T17	11		T190	3		T211	7
auto[1]	values[5]	values[2]	356	1			T164	122		T29	6		T167	5
auto[1]	values[5]	values[3]	225	1			T28	5		T261	9		T17	5
auto[1]	values[5]	values[4]	145	1			T164	12		T167	5		T183	9
auto[1]	values[5]	values[5]	385	1			T24	11		T27	13		T32	31
auto[1]	values[5]	values[6]	113	1			T20	10		T213	22		T150	9
auto[1]	values[5]	values[7]	213	1			T57	7		T28	6		T165	12
auto[1]	values[6]	values[0]	153	1			T164	46		T29	12		T150	9
auto[1]	values[6]	values[1]	93	1			T202	10		T229	8		T277	6
auto[1]	values[6]	values[2]	251	1			T278	12		T165	9		T168	13
auto[1]	values[6]	values[3]	59	1			T165	5		T205	20		T150	5
auto[1]	values[6]	values[4]	160	1			T29	8		T32	17		T279	4
auto[1]	values[6]	values[5]	180	1			T17	12		T165	12		T187	8
auto[1]	values[6]	values[6]	206	1			T20	7		T29	5		T203	7
auto[1]	values[6]	values[7]	115	1			T30	12		T32	5		T218	11
auto[1]	values[7]	values[0]	383	1			T167	6		T150	12		T202	17
auto[1]	values[7]	values[1]	82	1			T30	9		T165	7		T197	16
auto[1]	values[7]	values[2]	246	1			T27	5		T163	9		T167	8
auto[1]	values[7]	values[3]	175	1			T17	5		T150	14		T280	11
auto[1]	values[7]	values[4]	267	1			T5	14		T30	6		T17	13
auto[1]	values[7]	values[5]	159	1			T24	3		T218	7		T19	8
auto[1]	values[7]	values[6]	148	1			T4	18		T28	12		T163	15
auto[1]	values[7]	values[7]	232	1			T20	14		T27	4		T57	4