Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	319	1			T5	1		T20	1		T24	2
auto[ReadAddrCrossIntoMailbox]	235	1			T5	2		T20	3		T24	5
auto[ReadAddrCrossOutOfMailbox]	296	1			T5	2		T20	4		T24	7
auto[ReadAddrCrossAllMailbox]	181	1			T5	1		T20	2		T24	4
auto[ReadAddrOutsideMailbox]	2967	1			T4	6		T5	13		T11	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2022

1

T4

3

T5

11

T11

1

auto[1]

1976

1

T4

3

T5

8

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	662	1			T5	1		T11	2		T20	4
read_ops[0x0b]	675	1			T5	4		T12	2		T25	4
read_ops[0x3b]	634	1			T5	4		T12	2		T86	2
read_ops[0x6b]	655	1			T5	4		T87	2		T20	4
read_ops[0xbb]	684	1			T4	6		T5	2		T12	4
read_ops[0xeb]	688	1			T5	4		T20	6		T138	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T201	2		T29	1		T32	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T201	2		T30	1		T17	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T32	2		T167	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T24	1		T30	1		T17	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T20	1		T29	1		T218	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T24	1		T30	1		T32	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T29	1		T32	1		T208	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T20	1		T24	1		T29	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T5	1		T11	1		T20	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	234	1			T11	1		T20	1		T24	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T5	1		T24	1		T189	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T189	1		T247	3		T167	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T29	1		T30	1		T165	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T20	2		T32	2		T222	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T17	2		T221	2		T167	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T24	2		T57	2		T28	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T165	2		T228	1		T281	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T29	1		T32	1		T38	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T5	1		T12	1		T25	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	239	1			T5	2		T12	1		T25	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T57	1		T201	2		T29	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T201	2		T163	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T28	1		T19	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T5	1		T24	1		T163	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T24	1		T233	1		T263	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T20	1		T24	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T24	1		T250	1		T150	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T250	1		T211	1		T183	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	239	1			T5	2		T12	1		T86	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	237	1			T5	1		T12	1		T86	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T20	1		T57	1		T32	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T57	1		T28	1		T29	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T24	1		T57	1		T250	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T163	1		T29	1		T250	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T5	2		T20	1		T164	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T24	1		T28	2		T32	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T165	1		T218	1		T237	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T32	2		T237	1		T208	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	222	1			T5	1		T87	1		T20	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T5	1		T87	1		T20	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T24	1		T27	1		T28	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T57	1		T32	1		T165	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T20	1		T32	1		T19	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T57	1		T29	1		T150	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T24	1		T28	1		T165	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T27	1		T32	2		T165	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T27	1		T28	1		T282	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T20	1		T24	1		T57	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T4	3		T12	2		T25	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	246	1			T4	3		T5	2		T12	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T201	2		T167	1		T218	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T201	2		T17	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T5	1		T24	2		T28	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T28	1		T30	1		T226	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T163	1		T29	1		T32	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T20	1		T28	2		T226	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T5	1		T167	1		T226	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T24	1		T57	2		T28	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T5	1		T20	3		T138	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T5	1		T20	2		T138	1