Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2582277	1			T1	1		T2	8251		T3	3563
all_pins[1]	2582277	1			T1	1		T2	8251		T3	3563
all_pins[2]	2582277	1			T1	1		T2	8251		T3	3563
all_pins[3]	2582277	1			T1	1		T2	8251		T3	3563
all_pins[4]	2582277	1			T1	1		T2	8251		T3	3563
all_pins[5]	2582277	1			T1	1		T2	8251		T3	3563
all_pins[6]	2582277	1			T1	1		T2	8251		T3	3563
all_pins[7]	2582277	1			T1	1		T2	8251		T3	3563

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20611619	1			T1	8		T2	65991		T3	28504
values[0x1]	46597	1			T2	17		T53	5		T57	14
transitions[0x0=>0x1]	45816	1			T2	11		T53	5		T57	9
transitions[0x1=>0x0]	45827	1			T2	11		T53	5		T57	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2581804	1			T1	1		T2	8251		T3	3563
all_pins[0]	values[0x1]	473	1			T57	2		T29	1		T58	1
all_pins[0]	transitions[0x0=>0x1]	371	1			T57	2		T58	1		T32	5
all_pins[0]	transitions[0x1=>0x0]	170	1			T2	1		T53	2		T57	2
all_pins[1]	values[0x0]	2582005	1			T1	1		T2	8250		T3	3563
all_pins[1]	values[0x1]	272	1			T2	1		T53	2		T57	2
all_pins[1]	transitions[0x0=>0x1]	207	1			T53	2		T57	1		T59	1
all_pins[1]	transitions[0x1=>0x0]	173	1			T2	2		T57	1		T59	2
all_pins[2]	values[0x0]	2582039	1			T1	1		T2	8248		T3	3563
all_pins[2]	values[0x1]	238	1			T2	3		T57	2		T59	2
all_pins[2]	transitions[0x0=>0x1]	175	1			T2	3		T57	1		T59	2
all_pins[2]	transitions[0x1=>0x0]	113	1			T57	1		T29	2		T58	3
all_pins[3]	values[0x0]	2582101	1			T1	1		T2	8251		T3	3563
all_pins[3]	values[0x1]	176	1			T57	2		T29	2		T58	3
all_pins[3]	transitions[0x0=>0x1]	114	1			T57	1		T58	3		T32	2
all_pins[3]	transitions[0x1=>0x0]	140	1			T2	4		T53	1		T57	2
all_pins[4]	values[0x0]	2582075	1			T1	1		T2	8247		T3	3563
all_pins[4]	values[0x1]	202	1			T2	4		T53	1		T57	3
all_pins[4]	transitions[0x0=>0x1]	167	1			T2	2		T53	1		T57	2
all_pins[4]	transitions[0x1=>0x0]	1471	1			T2	2		T57	1		T59	2
all_pins[5]	values[0x0]	2580771	1			T1	1		T2	8247		T3	3563
all_pins[5]	values[0x1]	1506	1			T2	4		T57	2		T59	2
all_pins[5]	transitions[0x0=>0x1]	1135	1			T2	2		T57	1		T59	2
all_pins[5]	transitions[0x1=>0x0]	43198	1			T2	2		T53	2		T59	1
all_pins[6]	values[0x0]	2538708	1			T1	1		T2	8247		T3	3563
all_pins[6]	values[0x1]	43569	1			T2	4		T53	2		T57	1
all_pins[6]	transitions[0x0=>0x1]	43525	1			T2	3		T53	2		T57	1
all_pins[6]	transitions[0x1=>0x0]	117	1			T58	2		T32	4		T149	3
all_pins[7]	values[0x0]	2582116	1			T1	1		T2	8250		T3	3563
all_pins[7]	values[0x1]	161	1			T2	1		T58	3		T32	5
all_pins[7]	transitions[0x0=>0x1]	122	1			T2	1		T58	2		T32	4
all_pins[7]	transitions[0x1=>0x0]	445	1			T57	2		T29	1		T32	4