Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3399	1			T5	27		T12	26		T86	2
values[1]	3587	1			T5	44		T20	22		T24	67
values[2]	3392	1			T1	8		T20	28		T27	40
values[3]	3019	1			T5	22		T13	18		T87	8
values[4]	3810	1			T26	4		T24	65		T244	16
values[5]	2582	1			T5	21		T20	20		T24	86
values[6]	3209	1			T4	18		T14	14		T25	8
values[7]	2871	1			T11	18		T20	57		T24	42

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3591	1			T4	18		T5	27		T86	2
values[1]	2753	1			T87	8		T20	41		T100	4
values[2]	3115	1			T12	26		T20	23		T27	91
values[3]	3459	1			T13	18		T25	8		T20	58
values[4]	3967	1			T1	8		T5	21		T14	14
values[5]	3283	1			T5	20		T24	46		T27	20
values[6]	2832	1			T5	24		T11	18		T20	20
values[7]	2869	1			T5	22		T20	41		T24	60

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25427

1

T1

8

T4

18

T5

110

auto[1]

442

1

T5

4

T20

5

T24

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	485	1			T5	25		T86	2		T20	20
auto[0]	values[0]	values[1]	225	1			T100	4		T28	19		T30	20
auto[0]	values[0]	values[2]	491	1			T12	26		T20	23		T27	22
auto[0]	values[0]	values[3]	448	1			T164	34		T84	10		T259	26
auto[0]	values[0]	values[4]	512	1			T17	20		T32	23		T165	20
auto[0]	values[0]	values[5]	315	1			T247	6		T17	26		T19	20
auto[0]	values[0]	values[6]	345	1			T28	78		T163	24		T150	59
auto[0]	values[0]	values[7]	503	1			T20	18		T24	19		T165	40
auto[0]	values[1]	values[0]	345	1			T24	42		T19	20		T197	43
auto[0]	values[1]	values[1]	298	1			T274	2		T164	131		T29	20
auto[0]	values[1]	values[2]	628	1			T248	24		T167	35		T218	20
auto[0]	values[1]	values[3]	323	1			T20	22		T256	4		T163	20
auto[0]	values[1]	values[4]	754	1			T28	20		T29	20		T17	23
auto[0]	values[1]	values[5]	445	1			T5	20		T24	23		T28	20
auto[0]	values[1]	values[6]	350	1			T5	24		T235	25		T204	12
auto[0]	values[1]	values[7]	385	1			T264	10		T278	12		T167	20
auto[0]	values[2]	values[0]	421	1			T20	27		T189	10		T29	41
auto[0]	values[2]	values[1]	383	1			T29	20		T32	32		T150	18
auto[0]	values[2]	values[2]	350	1			T57	19		T246	12		T29	20
auto[0]	values[2]	values[3]	378	1			T57	22		T252	16		T168	24
auto[0]	values[2]	values[4]	660	1			T1	8		T27	19		T193	67
auto[0]	values[2]	values[5]	358	1			T28	44		T30	20		T167	43
auto[0]	values[2]	values[6]	454	1			T27	20		T28	26		T29	20
auto[0]	values[2]	values[7]	337	1			T57	20		T29	19		T30	22
auto[0]	values[3]	values[0]	418	1			T211	79		T183	28		T214	29
auto[0]	values[3]	values[1]	519	1			T87	8		T20	21		T24	20
auto[0]	values[3]	values[2]	328	1			T27	45		T57	20		T254	12
auto[0]	values[3]	values[3]	431	1			T13	18		T138	8		T32	19
auto[0]	values[3]	values[4]	202	1			T27	20		T28	19		T165	17
auto[0]	values[3]	values[5]	357	1			T28	41		T163	21		T30	20
auto[0]	values[3]	values[6]	451	1			T32	72		T205	18		T197	28
auto[0]	values[3]	values[7]	246	1			T5	21		T150	19		T183	37
auto[0]	values[4]	values[0]	596	1			T244	16		T162	60		T32	36
auto[0]	values[4]	values[1]	264	1			T165	37		T188	10		T229	27
auto[0]	values[4]	values[2]	477	1			T207	16		T163	20		T165	32
auto[0]	values[4]	values[3]	595	1			T24	21		T31	120		T17	24
auto[0]	values[4]	values[4]	705	1			T26	4		T24	23		T167	93
auto[0]	values[4]	values[5]	595	1			T166	18		T30	20		T32	20
auto[0]	values[4]	values[6]	211	1			T249	12		T30	20		T167	23
auto[0]	values[4]	values[7]	313	1			T24	19		T163	20		T32	20
auto[0]	values[5]	values[0]	290	1			T28	20		T163	22		T32	25
auto[0]	values[5]	values[1]	286	1			T102	10		T32	20		T165	23
auto[0]	values[5]	values[2]	257	1			T163	20		T202	22		T283	10
auto[0]	values[5]	values[3]	248	1			T167	45		T209	20		T151	24
auto[0]	values[5]	values[4]	332	1			T5	20		T24	43		T29	21
auto[0]	values[5]	values[5]	510	1			T24	23		T27	20		T32	20
auto[0]	values[5]	values[6]	272	1			T20	20		T27	20		T168	23
auto[0]	values[5]	values[7]	355	1			T24	20		T29	22		T257	4
auto[0]	values[6]	values[0]	468	1			T4	18		T24	23		T269	2
auto[0]	values[6]	values[1]	503	1			T20	20		T164	61		T201	20
auto[0]	values[6]	values[2]	220	1			T167	27		T202	33		T235	20
auto[0]	values[6]	values[3]	534	1			T25	8		T29	20		T32	20
auto[0]	values[6]	values[4]	340	1			T14	14		T27	22		T215	20
auto[0]	values[6]	values[5]	378	1			T17	28		T238	20		T199	20
auto[0]	values[6]	values[6]	390	1			T137	16		T250	4		T165	20
auto[0]	values[6]	values[7]	324	1			T17	20		T213	22		T284	12
auto[0]	values[7]	values[0]	494	1			T24	19		T271	6		T164	20
auto[0]	values[7]	values[1]	226	1			T17	21		T165	20		T214	30
auto[0]	values[7]	values[2]	312	1			T27	20		T17	23		T255	8
auto[0]	values[7]	values[3]	452	1			T20	34		T265	16		T17	23
auto[0]	values[7]	values[4]	392	1			T24	21		T262	8		T212	2
auto[0]	values[7]	values[5]	274	1			T165	20		T208	20		T241	91
auto[0]	values[7]	values[6]	300	1			T11	18		T57	20		T218	20
auto[0]	values[7]	values[7]	369	1			T20	21		T150	24		T263	50
auto[1]	values[0]	values[0]	11	1			T5	2		T229	2		T214	3
auto[1]	values[0]	values[1]	7	1			T28	1		T285	4		T286	2
auto[1]	values[0]	values[2]	11	1			T27	2		T183	3		T277	1
auto[1]	values[0]	values[3]	8	1			T150	1		T229	1		T287	6
auto[1]	values[0]	values[4]	11	1			T218	3		T150	3		T214	1
auto[1]	values[0]	values[5]	9	1			T17	2		T211	2		T288	4
auto[1]	values[0]	values[6]	12	1			T28	2		T202	2		T235	2
auto[1]	values[0]	values[7]	6	1			T20	2		T24	1		T19	1
auto[1]	values[1]	values[0]	8	1			T24	2		T197	2		T263	1
auto[1]	values[1]	values[1]	1	1			T233	1		-	-		-	-
auto[1]	values[1]	values[2]	8	1			T289	2		T125	1		T290	1
auto[1]	values[1]	values[3]	4	1			T32	2		T241	2		-	-
auto[1]	values[1]	values[4]	18	1			T29	2		T202	2		T291	2
auto[1]	values[1]	values[5]	2	1			T165	1		T292	1		-	-
auto[1]	values[1]	values[6]	15	1			T204	8		T272	2		T39	4
auto[1]	values[1]	values[7]	3	1			T273	1		T288	2		-	-
auto[1]	values[2]	values[0]	10	1			T20	1		T17	3		T19	1
auto[1]	values[2]	values[1]	7	1			T32	2		T150	2		T228	2
auto[1]	values[2]	values[2]	5	1			T57	1		T17	1		T168	3
auto[1]	values[2]	values[3]	3	1			T229	3		-	-		-	-
auto[1]	values[2]	values[4]	14	1			T27	1		T30	1		T202	3
auto[1]	values[2]	values[5]	7	1			T30	1		T183	3		T208	1
auto[1]	values[2]	values[6]	4	1			T28	1		T293	3		-	-
auto[1]	values[2]	values[7]	1	1			T29	1		-	-		-	-
auto[1]	values[3]	values[0]	10	1			T211	2		T214	2		T289	1
auto[1]	values[3]	values[1]	12	1			T57	2		T215	2		T184	1
auto[1]	values[3]	values[2]	6	1			T27	2		T214	1		T38	1
auto[1]	values[3]	values[3]	6	1			T32	1		T214	1		T286	1
auto[1]	values[3]	values[4]	6	1			T28	1		T165	3		T277	1
auto[1]	values[3]	values[5]	6	1			T28	3		T275	1		T39	1
auto[1]	values[3]	values[6]	17	1			T32	1		T205	2		T184	1
auto[1]	values[3]	values[7]	4	1			T5	1		T150	1		T183	1
auto[1]	values[4]	values[0]	8	1			T150	1		T263	2		T209	2
auto[1]	values[4]	values[1]	4	1			T165	1		T273	2		T290	1
auto[1]	values[4]	values[2]	9	1			T163	2		T165	1		T263	1
auto[1]	values[4]	values[3]	6	1			T24	1		T31	2		T294	2
auto[1]	values[4]	values[4]	8	1			T150	2		T295	1		T296	5
auto[1]	values[4]	values[5]	11	1			T297	1		T298	1		T294	5
auto[1]	values[4]	values[6]	3	1			T30	1		T167	1		T299	1
auto[1]	values[4]	values[7]	5	1			T24	1		T229	1		T300	3
auto[1]	values[5]	values[0]	6	1			T163	3		T272	1		T301	2
auto[1]	values[5]	values[1]	1	1			T288	1		-	-		-	-
auto[1]	values[5]	values[2]	3	1			T202	1		T275	2		-	-
auto[1]	values[5]	values[3]	4	1			T167	1		T151	2		T125	1
auto[1]	values[5]	values[4]	6	1			T5	1		T29	3		T301	2
auto[1]	values[5]	values[5]	6	1			T263	2		T275	1		T277	2
auto[1]	values[5]	values[6]	3	1			T200	1		T243	1		T302	1
auto[1]	values[5]	values[7]	3	1			T211	1		T277	1		T281	1
auto[1]	values[6]	values[0]	5	1			T28	1		T32	1		T228	1
auto[1]	values[6]	values[1]	9	1			T164	1		T241	1		T38	1
auto[1]	values[6]	values[2]	9	1			T202	3		T272	6		-	-
auto[1]	values[6]	values[3]	12	1			T150	6		T297	1		T231	1
auto[1]	values[6]	values[4]	5	1			T27	2		T243	1		T303	2
auto[1]	values[6]	values[5]	6	1			T238	2		T228	1		T304	2
auto[1]	values[6]	values[6]	2	1			T167	1		T229	1		-	-
auto[1]	values[6]	values[7]	4	1			T17	2		T291	1		T305	1
auto[1]	values[7]	values[0]	16	1			T24	2		T29	2		T165	2
auto[1]	values[7]	values[1]	8	1			T17	3		T214	1		T286	3
auto[1]	values[7]	values[2]	1	1			T125	1		-	-		-	-
auto[1]	values[7]	values[3]	7	1			T20	2		T32	3		T289	1
auto[1]	values[7]	values[4]	2	1			T197	1		T272	1		-	-
auto[1]	values[7]	values[5]	4	1			T241	1		T184	3		-	-
auto[1]	values[7]	values[6]	3	1			T184	2		T281	1		-	-
auto[1]	values[7]	values[7]	11	1			T263	2		T292	1		T270	1