Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1808

1

T2

12

T5

7

T8

5

auto[1]

1684

1

T2

8

T5

2

T8

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1871

1

T2

20

T5

9

T8

10

auto[1]

1621

1

T10

1

T15

25

T16

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2767

1

T2

18

T5

5

T8

6

auto[1]

725

1

T2

2

T5

4

T8

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	660	1			T2	9		T5	2		T8	2
valid[1]	716	1			T2	4		T5	2		T8	2
valid[2]	691	1			T2	1		T5	1		T8	2
valid[3]	701	1			T2	4		T8	2		T9	4
valid[4]	724	1			T2	2		T5	4		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	118	1			T2	6		T5	1		T9	1
auto[0]	auto[0]	valid[0]	auto[1]	155	1			T15	2		T16	1		T81	2
auto[0]	auto[0]	valid[1]	auto[0]	125	1			T2	2		T5	1		T8	1
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T15	1		T37	1		T80	2
auto[0]	auto[0]	valid[2]	auto[0]	103	1			T9	2		T10	1		T24	1
auto[0]	auto[0]	valid[2]	auto[1]	188	1			T15	4		T16	1		T37	1
auto[0]	auto[0]	valid[3]	auto[0]	113	1			T2	2		T8	1		T9	1
auto[0]	auto[0]	valid[3]	auto[1]	158	1			T15	2		T80	3		T81	1
auto[0]	auto[0]	valid[4]	auto[0]	112	1			T5	1		T8	1		T9	1
auto[0]	auto[0]	valid[4]	auto[1]	183	1			T15	2		T80	1		T81	3
auto[0]	auto[1]	valid[0]	auto[0]	92	1			T2	1		T5	1		T8	1
auto[0]	auto[1]	valid[0]	auto[1]	154	1			T10	1		T15	2		T16	1
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T2	2		T8	1		T9	2
auto[0]	auto[1]	valid[1]	auto[1]	165	1			T15	3		T80	2		T81	2
auto[0]	auto[1]	valid[2]	auto[0]	128	1			T2	1		T8	1		T9	3
auto[0]	auto[1]	valid[2]	auto[1]	133	1			T15	2		T81	2		T57	2
auto[0]	auto[1]	valid[3]	auto[0]	125	1			T2	2		T9	1		T23	3
auto[0]	auto[1]	valid[3]	auto[1]	157	1			T15	5		T80	2		T329	1
auto[0]	auto[1]	valid[4]	auto[0]	112	1			T2	2		T5	1		T21	1
auto[0]	auto[1]	valid[4]	auto[1]	169	1			T15	2		T16	2		T80	2
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T2	2		T9	2		T20	1
auto[1]	auto[0]	valid[1]	auto[0]	82	1			T5	1		T57	1		T196	1
auto[1]	auto[0]	valid[2]	auto[0]	75	1			T5	1		T8	1		T9	1
auto[1]	auto[0]	valid[3]	auto[0]	80	1			T8	1		T9	1		T157	1
auto[1]	auto[0]	valid[4]	auto[0]	78	1			T5	2		T10	1		T23	1
auto[1]	auto[1]	valid[0]	auto[0]	62	1			T8	1		T22	1		T20	1
auto[1]	auto[1]	valid[1]	auto[0]	67	1			T20	1		T323	1		T29	1
auto[1]	auto[1]	valid[2]	auto[0]	64	1			T20	2		T24	1		T27	1
auto[1]	auto[1]	valid[3]	auto[0]	68	1			T9	1		T10	1		T24	2
auto[1]	auto[1]	valid[4]	auto[0]	70	1			T8	1		T9	1		T157	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal