Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49451

1

T2

488

T3

8

T5

246

auto[1]

17318

1

T10

31

T15

365

T16

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48884

1

T2

342

T3

6

T5

170

auto[1]

17885

1

T2

146

T3

2

T5

76

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34207	1			T2	253		T3	4		T5	138
others[1]	5687	1			T2	32		T5	15		T8	34
others[2]	5689	1			T2	53		T3	1		T5	22
others[3]	6398	1			T2	46		T3	1		T5	16
interest[1]	3683	1			T2	21		T3	1		T5	12
interest[4]	22291	1			T2	154		T3	3		T5	83
interest[64]	11105	1			T2	83		T3	1		T5	43

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16117	1			T2	183		T3	4		T5	90
auto[0]	auto[0]	others[1]	2692	1			T2	18		T5	10		T8	26
auto[0]	auto[0]	others[2]	2691	1			T2	37		T3	1		T5	18
auto[0]	auto[0]	others[3]	3046	1			T2	36		T5	12		T8	33
auto[0]	auto[0]	interest[1]	1733	1			T2	13		T3	1		T5	7
auto[0]	auto[0]	interest[4]	10411	1			T2	114		T3	3		T5	54
auto[0]	auto[0]	interest[64]	5287	1			T2	55		T5	33		T8	38
auto[0]	auto[1]	others[0]	8976	1			T10	14		T15	180		T16	5
auto[0]	auto[1]	others[1]	1469	1			T10	2		T15	33		T22	2
auto[0]	auto[1]	others[2]	1434	1			T10	6		T15	32		T22	2
auto[0]	auto[1]	others[3]	1613	1			T10	4		T15	38		T22	3
auto[0]	auto[1]	interest[1]	942	1			T15	21		T22	1		T80	14
auto[0]	auto[1]	interest[4]	5915	1			T10	8		T15	120		T16	5
auto[0]	auto[1]	interest[64]	2884	1			T10	5		T15	61		T22	3
auto[1]	auto[0]	others[0]	9114	1			T2	70		T5	48		T7	2
auto[1]	auto[0]	others[1]	1526	1			T2	14		T5	5		T8	8
auto[1]	auto[0]	others[2]	1564	1			T2	16		T5	4		T8	12
auto[1]	auto[0]	others[3]	1739	1			T2	10		T3	1		T5	4
auto[1]	auto[0]	interest[1]	1008	1			T2	8		T5	5		T8	6
auto[1]	auto[0]	interest[4]	5965	1			T2	40		T5	29		T7	2
auto[1]	auto[0]	interest[64]	2934	1			T2	28		T3	1		T5	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal