Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	732	1			T2	7		T53	7		T57	7
all_values[1]	732	1			T2	7		T53	7		T57	7
all_values[2]	732	1			T2	7		T53	7		T57	7
all_values[3]	732	1			T2	7		T53	7		T57	7
all_values[4]	732	1			T2	7		T53	7		T57	7
all_values[5]	732	1			T2	7		T53	7		T57	7
all_values[6]	732	1			T2	7		T53	7		T57	7
all_values[7]	732	1			T2	7		T53	7		T57	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3126

1

T2

30

T53

28

T57

25

auto[1]

2730

1

T2

26

T53

28

T57

31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2340

1

T2

18

T53

38

T57

24

auto[1]

3516

1

T2

38

T53

18

T57

32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3338

1

T2

28

T53

42

T57

35

auto[1]

2518

1

T2

28

T53

14

T57

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	170	1			T2	1		T53	2		T57	2
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T59	1		T58	2		T32	1
all_values[0]	auto[0]	auto[1]	auto[0]	131	1			T2	5		T53	3		T57	3
all_values[0]	auto[0]	auto[1]	auto[1]	59	1			T58	1		T32	4		T161	1
all_values[0]	auto[1]	auto[0]	auto[1]	171	1			T2	1		T53	2		T59	2
all_values[0]	auto[1]	auto[1]	auto[1]	123	1			T57	2		T29	1		T58	3
all_values[1]	auto[0]	auto[0]	auto[0]	143	1			T2	1		T53	2		T59	4
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T2	1		T57	2		T29	1
all_values[1]	auto[0]	auto[1]	auto[0]	120	1			T53	2		T59	1		T58	3
all_values[1]	auto[0]	auto[1]	auto[1]	56	1			T53	1		T58	1		T32	1
all_values[1]	auto[1]	auto[0]	auto[1]	189	1			T2	4		T57	3		T59	1
all_values[1]	auto[1]	auto[1]	auto[1]	142	1			T2	1		T53	2		T57	2
all_values[2]	auto[0]	auto[0]	auto[0]	136	1			T2	1		T53	2		T57	1
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T2	2		T57	1		T59	1
all_values[2]	auto[0]	auto[1]	auto[0]	115	1			T53	3		T57	1		T59	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T2	2		T57	2		T32	3
all_values[2]	auto[1]	auto[0]	auto[1]	173	1			T53	2		T57	2		T59	1
all_values[2]	auto[1]	auto[1]	auto[1]	154	1			T2	2		T59	3		T58	5
all_values[3]	auto[0]	auto[0]	auto[0]	162	1			T2	2		T53	2		T57	1
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T57	2		T32	1		T18	1
all_values[3]	auto[0]	auto[1]	auto[0]	130	1			T2	1		T53	3		T57	2
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T53	1		T29	1		T58	1
all_values[3]	auto[1]	auto[0]	auto[1]	155	1			T2	3		T53	1		T59	3
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T2	1		T57	2		T29	1
all_values[4]	auto[0]	auto[0]	auto[0]	134	1			T53	3		T59	1		T32	5
all_values[4]	auto[0]	auto[0]	auto[1]	59	1			T2	1		T58	1		T32	1
all_values[4]	auto[0]	auto[1]	auto[0]	144	1			T53	1		T57	3		T59	2
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T2	2		T53	1		T57	2
all_values[4]	auto[1]	auto[0]	auto[1]	150	1			T2	3		T53	1		T57	2
all_values[4]	auto[1]	auto[1]	auto[1]	167	1			T2	1		T53	1		T59	3
all_values[5]	auto[0]	auto[0]	auto[0]	232	1			T2	2		T53	5		T57	1
all_values[5]	auto[0]	auto[1]	auto[0]	199	1			T2	1		T53	1		T57	3
all_values[5]	auto[1]	auto[0]	auto[1]	158	1			T2	2		T53	1		T57	1
all_values[5]	auto[1]	auto[1]	auto[1]	143	1			T2	2		T57	2		T59	2
all_values[6]	auto[0]	auto[0]	auto[0]	135	1			T53	2		T57	1		T59	2
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T2	1		T58	1		T148	2
all_values[6]	auto[0]	auto[1]	auto[0]	105	1			T53	1		T57	4		T59	1
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T53	1		T29	1		T58	3
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T2	2		T53	2		T57	1
all_values[6]	auto[1]	auto[1]	auto[1]	152	1			T2	4		T53	1		T57	1
all_values[7]	auto[0]	auto[0]	auto[0]	166	1			T2	2		T53	1		T59	2
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T57	2		T59	2		T32	4
all_values[7]	auto[0]	auto[1]	auto[0]	118	1			T2	2		T53	5		T57	2
all_values[7]	auto[0]	auto[1]	auto[1]	56	1			T2	1		T58	1		T149	1
all_values[7]	auto[1]	auto[0]	auto[1]	163	1			T2	1		T57	3		T59	2
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T2	1		T53	1		T58	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal