Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2621598	1			T1	4097		T2	1		T3	899
all_values[1]	2621598	1			T1	4097		T2	1		T3	899
all_values[2]	2621598	1			T1	4097		T2	1		T3	899
all_values[3]	2621598	1			T1	4097		T2	1		T3	899
all_values[4]	2621598	1			T1	4097		T2	1		T3	899
all_values[5]	2621598	1			T1	4097		T2	1		T3	899
all_values[6]	2621598	1			T1	4097		T2	1		T3	899
all_values[7]	2621598	1			T1	4097		T2	1		T3	899

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20352581

1

T1

32776

T2

8

T3

7192

auto[1]

620203

1

T37

46049

T54

57

T32

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949781

1

T1

32699

T2

8

T3

7192

auto[1]

23003

1

T1

77

T9

150

T16

208

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2573319	1			T1	4071		T2	1		T3	899
all_values[0]	auto[0]	auto[1]	11705	1			T1	26		T9	92		T16	91
all_values[0]	auto[1]	auto[0]	36246	1			T37	2		T54	2		T32	1
all_values[0]	auto[1]	auto[1]	328	1			T54	5		T33	9		T58	1
all_values[1]	auto[0]	auto[0]	2517238	1			T1	4071		T2	1		T3	899
all_values[1]	auto[0]	auto[1]	5973	1			T1	26		T9	48		T16	91
all_values[1]	auto[1]	auto[0]	97906	1			T37	11366		T54	4		T32	2
all_values[1]	auto[1]	auto[1]	481	1			T37	146		T54	4		T32	2
all_values[2]	auto[0]	auto[0]	2596055	1			T1	4072		T2	1		T3	899
all_values[2]	auto[0]	auto[1]	2393	1			T1	25		T9	10		T16	26
all_values[2]	auto[1]	auto[0]	22952	1			T37	2		T54	1		T32	2
all_values[2]	auto[1]	auto[1]	198	1			T37	1		T54	4		T32	2
all_values[3]	auto[0]	auto[0]	2599032	1			T1	4097		T2	1		T3	899
all_values[3]	auto[0]	auto[1]	194	1			T110	3		T37	1		T54	2
all_values[3]	auto[1]	auto[0]	22187	1			T37	11510		T54	10		T32	1
all_values[3]	auto[1]	auto[1]	185	1			T37	1		T54	1		T32	1
all_values[4]	auto[0]	auto[0]	2486994	1			T1	4097		T2	1		T3	899
all_values[4]	auto[0]	auto[1]	181	1			T54	3		T33	1		T79	2
all_values[4]	auto[1]	auto[0]	134251	1			T37	11508		T54	1		T32	5
all_values[4]	auto[1]	auto[1]	172	1			T37	1		T54	2		T33	4
all_values[5]	auto[0]	auto[0]	2491990	1			T1	4097		T2	1		T3	899
all_values[5]	auto[0]	auto[1]	297	1			T177	1		T178	1		T179	1
all_values[5]	auto[1]	auto[0]	129130	1			T54	6		T32	4		T33	7
all_values[5]	auto[1]	auto[1]	181	1			T54	5		T33	3		T58	1
all_values[6]	auto[0]	auto[0]	2555262	1			T1	4097		T2	1		T3	899
all_values[6]	auto[0]	auto[1]	178	1			T37	1		T54	2		T33	3
all_values[6]	auto[1]	auto[0]	65999	1			T37	2		T54	3		T32	1
all_values[6]	auto[1]	auto[1]	159	1			T54	3		T32	2		T33	1
all_values[7]	auto[0]	auto[0]	2511571	1			T1	4097		T2	1		T3	899
all_values[7]	auto[0]	auto[1]	199	1			T37	1		T54	2		T32	2
all_values[7]	auto[1]	auto[0]	109649	1			T37	11508		T54	4		T33	10
all_values[7]	auto[1]	auto[1]	179	1			T37	2		T54	2		T33	3