Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28828	1			T1	66		T2	2		T3	300
auto[SpiFlashAddrCfg]	6113	1			T1	15		T2	4		T3	29
auto[SpiFlashAddr3b]	7319	1			T1	24		T2	4		T3	26
auto[SpiFlashAddr4b]	6046	1			T1	14		T3	25		T4	48

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26536

1

T1

84

T2

10

T3

200

auto[1]

21770

1

T1

35

T3

180

T4

418

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26419

1

T1

45

T2

4

T3

109

auto[1]

21887

1

T1

74

T2

6

T3

271

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32696	1			T1	73		T2	2		T3	333
values[1]	897	1			T3	2		T4	7		T9	4
values[2]	1187	1			T1	3		T3	6		T4	6
values[3]	1176	1			T3	3		T4	11		T9	13
values[4]	1222	1			T1	2		T3	7		T4	9
values[5]	1156	1			T1	11		T2	4		T3	7
values[6]	1101	1			T1	3		T3	3		T4	17
values[7]	1103	1			T1	4		T3	1		T4	3
values[8]	7768	1			T1	23		T2	4		T3	18

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22997

1

T2

10

T9

377

T10

18

auto[1]

25309

1

T1

119

T3

380

T4

611

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

46545

1

T1

113

T2

10

T3

370

write

1761

1

T1

6

T3

10

T4

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15744

1

T1

42

T2

8

T3

59

valids[0x1]

32562

1

T1

77

T2

2

T3

321

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1289	1			T1	2		T2	2		T3	7
internal_process_ops[0x5a]	1296	1			T1	5		T3	8		T4	7
internal_process_ops[0x05]	17409	1			T1	26		T3	264		T4	362
internal_process_ops[0x35]	1322	1			T1	5		T3	10		T4	8
internal_process_ops[0x15]	1339	1			T1	6		T3	3		T4	9
internal_process_ops[0x03]	840	1			T1	3		T3	2		T4	5
internal_process_ops[0x0b]	841	1			T3	1		T4	4		T9	5
internal_process_ops[0x3b]	861	1			T1	2		T2	4		T3	2
internal_process_ops[0x6b]	844	1			T1	1		T2	2		T4	3
internal_process_ops[0xbb]	823	1			T1	1		T4	1		T9	10
internal_process_ops[0xeb]	848	1			T2	2		T3	3		T4	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47473

1

T1

116

T2

10

T3

374

auto[1]

833

1

T1

3

T3

6

T4

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46543

1

T1

113

T2

10

T3

361

auto[1]

1763

1

T1

6

T3

19

T4

18

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7607

1

T2

2

T9

114

T10

18

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4845

1

T9

124

T25

52

T26

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1607

1

T2

4

T9

19

T24

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1457

1

T9

31

T25

17

T26

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1960

1

T2

4

T9

28

T24

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1723

1

T9

20

T25

22

T26

33

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1567

1

T9

8

T24

4

T74

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1434

1

T9

21

T25

18

T26

18

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

60

1

T9

1

T26

2

T168

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

36

1

T26

2

T35

1

T166

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

60

1

T26

2

T34

1

T35

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

56

1

T31

2

T33

2

T34

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

69

1

T25

3

T168

2

T169

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

40

1

T29

2

T33

1

T170

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

59

1

T25

2

T26

2

T32

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

45

1

T25

1

T31

3

T32

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

71

1

T9

8

T29

1

T171

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

34

1

T9

1

T25

1

T31

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

41

1

T26

4

T29

1

T170

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

47

1

T9

1

T31

2

T170

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

46

1

T25

1

T32

1

T35

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

45

1

T9

1

T25

3

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

41

1

T29

3

T32

1

T34

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

47

1

T30

1

T172

1

T34

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8569

1

T1

50

T3

164

T4

100

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7365

1

T1

16

T3

132

T4

350

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1358

1

T1

9

T3

15

T4

39

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1239

1

T1

6

T3

10

T4

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1628

1

T1

12

T3

10

T4

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1582

1

T1

7

T3

14

T4

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1367

1

T1

10

T3

9

T4

25

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1237

1

T1

3

T3

16

T4

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

44

1

T22

1

T17

4

T23

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

65

1

T3

2

T16

1

T39

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

57

1

T3

2

T173

5

T174

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

64

1

T4

2

T23

3

T175

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

54

1

T22

1

T16

1

T39

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

67

1

T4

1

T9

1

T17

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

55

1

T3

2

T22

3

T23

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T3

2

T22

3

T37

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

68

1

T4

1

T22

2

T16

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

46

1

T1

2

T174

3

T176

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

60

1

T1

3

T4

1

T17

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

59

1

T3

2

T4

2

T16

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

76

1

T4

3

T22

3

T23

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

52

1

T1

1

T4

2

T22

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

67

1

T17

1

T23

2

T39

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

67

1

T22

4

T16

1

T17

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3145	1			T9	32		T13	2		T25	34
auto[0]	values[0]	valids[0x1]	11386	1			T2	2		T9	227		T10	18
auto[0]	values[1]	valids[0x1]	427	1			T9	4		T28	4		T25	3
auto[0]	values[2]	valids[0x0]	433	1			T9	3		T28	6		T25	2
auto[0]	values[2]	valids[0x1]	240	1			T9	1		T25	1		T26	2
auto[0]	values[3]	valids[0x0]	419	1			T9	5		T28	2		T25	8
auto[0]	values[3]	valids[0x1]	236	1			T9	6		T24	4		T25	4
auto[0]	values[4]	valids[0x0]	410	1			T9	5		T25	7		T92	2
auto[0]	values[4]	valids[0x1]	264	1			T9	5		T25	5		T26	1
auto[0]	values[5]	valids[0x0]	425	1			T2	4		T9	12		T24	2
auto[0]	values[5]	valids[0x1]	210	1			T24	2		T36	2		T25	3
auto[0]	values[6]	valids[0x0]	373	1			T9	3		T25	2		T26	1
auto[0]	values[6]	valids[0x1]	222	1			T74	4		T25	2		T26	3
auto[0]	values[7]	valids[0x0]	436	1			T9	9		T25	2		T26	5
auto[0]	values[7]	valids[0x1]	208	1			T25	4		T26	4		T29	1
auto[0]	values[8]	valids[0x0]	2667	1			T2	4		T9	40		T24	4
auto[0]	values[8]	valids[0x1]	1496	1			T9	25		T25	15		T26	11
auto[1]	values[0]	valids[0x0]	3536	1			T1	20		T3	29		T4	41
auto[1]	values[0]	valids[0x1]	14629	1			T1	53		T3	304		T4	433
auto[1]	values[1]	valids[0x1]	470	1			T3	2		T4	7		T22	3
auto[1]	values[2]	valids[0x0]	311	1			T1	2		T3	5		T4	4
auto[1]	values[2]	valids[0x1]	203	1			T1	1		T3	1		T4	2
auto[1]	values[3]	valids[0x0]	291	1			T3	2		T4	6		T9	1
auto[1]	values[3]	valids[0x1]	230	1			T3	1		T4	5		T9	1
auto[1]	values[4]	valids[0x0]	352	1			T1	1		T3	7		T4	5
auto[1]	values[4]	valids[0x1]	196	1			T1	1		T4	4		T22	6
auto[1]	values[5]	valids[0x0]	282	1			T1	6		T3	4		T4	4
auto[1]	values[5]	valids[0x1]	239	1			T1	5		T3	3		T4	3
auto[1]	values[6]	valids[0x0]	303	1			T1	1		T3	1		T4	15
auto[1]	values[6]	valids[0x1]	203	1			T1	2		T3	2		T4	2
auto[1]	values[7]	valids[0x0]	284	1			T1	3		T3	1		T4	1
auto[1]	values[7]	valids[0x1]	175	1			T1	1		T4	2		T22	5
auto[1]	values[8]	valids[0x0]	2077	1			T1	9		T3	10		T4	44
auto[1]	values[8]	valids[0x1]	1528	1			T1	14		T3	8		T4	33