Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2833987

1

T1

4757

T2

1187

T3

5054

auto[1]

16150

1

T1

19

T3

260

T4

351

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

965044

1

T1

40

T2

1187

T3

63

auto[1]

1885093

1

T1

4736

T3

5251

T4

7938

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	516230	1			T1	326		T2	93		T3	1
auto[524288:1048575]	328069	1			T1	14		T2	224		T3	31
auto[1048576:1572863]	351244	1			T2	185		T3	68		T4	257
auto[1572864:2097151]	350113	1			T1	2		T2	2		T3	454
auto[2097152:2621439]	304551	1			T1	2345		T2	116		T3	596
auto[2621440:3145727]	331634	1			T1	644		T2	159		T3	316
auto[3145728:3670015]	328947	1			T1	1275		T2	112		T3	474
auto[3670016:4194303]	339349	1			T1	170		T2	296		T3	3374

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1904739

1

T1

4775

T2

24

T3

5297

auto[1]

945398

1

T1

1

T2

1163

T3

17

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2443738

1

T1

4629

T2

1187

T3

5090

auto[1]

406399

1

T1

147

T3

224

T4

8

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	211670	1			T1	4		T2	93		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	246750	1			T1	305		T4	772		T9	130
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	125616	1			T1	4		T2	224		T3	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	158960	1			T1	7		T3	4		T4	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	113115	1			T2	185		T3	4		T4	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	194774	1			T3	54		T4	135		T9	129
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	91451	1			T1	2		T2	2		T3	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	204742	1			T3	266		T4	2389		T9	2874
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	82004	1			T1	9		T2	116		T3	7
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	173536	1			T1	2199		T3	517		T4	4299
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	102176	1			T1	3		T2	159		T3	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	173938	1			T1	640		T3	286		T9	3941
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	118963	1			T1	5		T2	112		T3	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	150398	1			T1	1270		T3	387		T4	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	113989	1			T1	2		T2	296		T3	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	168556	1			T1	168		T3	3364		T4	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	406	1			T1	3		T4	1		T16	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	54654	1			T1	6		T16	513		T17	515
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	453	1			T9	2		T22	2		T16	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	40486	1			T9	1		T22	1		T17	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1371	1			T4	1		T9	1		T17	11
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	40281	1			T4	4		T9	1		T17	3730
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	420	1			T3	6		T4	2		T9	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51508	1			T3	131		T9	2645		T17	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	476	1			T1	1		T22	4		T17	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46685	1			T1	128		T22	1837		T17	512
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	266	1			T1	1		T22	4		T23	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53324	1			T22	1697		T23	2754		T39	384
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	431	1			T3	2		T22	4		T16	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	57838	1			T3	1		T9	384		T22	257
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	469	1			T16	1		T175	1		T231	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54281	1			T16	915		T23	12		T31	516
auto[1]	auto[0]	auto[0:524287]	auto[0]	228	1			T4	2		T9	2		T22	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	2049	1			T4	24		T9	51		T22	106
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	190	1			T1	2		T3	2		T9	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1808	1			T1	1		T3	21		T22	11
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	182	1			T3	2		T4	4		T9	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1177	1			T3	8		T4	105		T9	68
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	150	1			T3	1		T4	3		T22	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1453	1			T3	13		T4	46		T22	65
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	148	1			T1	3		T3	5		T4	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1319	1			T1	5		T3	67		T4	80
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	195	1			T3	2		T16	1		T23	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1465	1			T3	23		T16	2		T25	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	130	1			T3	3		T4	2		T9	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	882	1			T3	23		T4	30		T9	9
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	170	1			T3	1		T4	3		T9	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1554	1			T3	5		T4	48		T9	17
auto[1]	auto[1]	auto[0:524287]	auto[0]	51	1			T1	1		T16	1		T17	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	422	1			T1	7		T16	1		T17	15
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	55	1			T9	1		T22	1		T17	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	501	1			T9	4		T17	40		T39	11
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	49	1			T9	1		T37	1		T29	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	295	1			T37	2		T54	19		T166	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	64	1			T3	2		T17	1		T23	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	325	1			T3	30		T17	6		T23	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	52	1			T37	2		T54	1		T32	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	331	1			T37	12		T32	6		T176	30
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	34	1			T22	1		T23	1		T26	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	236	1			T22	15		T23	5		T34	35
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	35	1			T3	1		T22	1		T16	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	270	1			T3	51		T22	28		T16	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	35	1			T32	1		T194	1		T174	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	295	1			T32	5		T194	26		T232	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1487950	1			T1	4617		T2	24		T3	4906
auto[0]	auto[0]	auto[1]	942688	1			T1	1		T2	1163		T3	8
auto[0]	auto[1]	auto[0]	400968	1			T1	139		T3	139		T4	8
auto[0]	auto[1]	auto[1]	2381	1			T3	1		T9	1		T22	2
auto[1]	auto[0]	auto[0]	12830	1			T1	11		T3	169		T4	350
auto[1]	auto[0]	auto[1]	270	1			T3	7		T4	1		T22	1
auto[1]	auto[1]	auto[0]	2991	1			T1	8		T3	83		T9	6
auto[1]	auto[1]	auto[1]	59	1			T3	1		T23	2		T194	1