Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13142

1

T2

10

T9

180

T10

18

auto[1]

9855

1

T9

197

T25

112

T26

93

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2606	1			T2	10		T9	77		T25	48
values[1]	2788	1			T9	90		T24	14		T25	32
values[2]	2996	1			T9	20		T74	14		T25	27
values[3]	2915	1			T9	29		T26	45		T233	4
values[4]	2945	1			T9	20		T13	2		T25	29
values[5]	3239	1			T9	91		T25	26		T26	40
values[6]	2562	1			T10	18		T28	16		T25	44
values[7]	2946	1			T9	50		T36	2		T25	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2697	1			T9	97		T36	2		T74	14
values[1]	2826	1			T9	31		T25	20		T92	14
values[2]	2907	1			T9	110		T25	28		T88	2
values[3]	2816	1			T9	50		T24	14		T26	20
values[4]	3240	1			T9	20		T10	18		T28	16
values[5]	2809	1			T25	24		T26	90		T29	62
values[6]	3440	1			T9	29		T25	82		T26	23
values[7]	2262	1			T2	10		T9	40		T13	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	127	1			T9	6		T33	11		T204	9
auto[0]	values[0]	values[1]	220	1			T92	14		T26	28		T29	8
auto[0]	values[0]	values[2]	248	1			T25	23		T88	2		T29	11
auto[0]	values[0]	values[3]	219	1			T32	11		T199	12		T189	7
auto[0]	values[0]	values[4]	211	1			T32	51		T167	8		T69	16
auto[0]	values[0]	values[5]	177	1			T29	21		T30	8		T34	7
auto[0]	values[0]	values[6]	86	1			T31	13		T203	4		T234	17
auto[0]	values[0]	values[7]	266	1			T2	10		T25	6		T235	2
auto[0]	values[1]	values[0]	306	1			T25	14		T29	20		T194	15
auto[0]	values[1]	values[1]	81	1			T33	13		T170	10		T236	4
auto[0]	values[1]	values[2]	193	1			T9	84		T216	2		T237	16
auto[0]	values[1]	values[3]	205	1			T24	14		T211	10		T204	13
auto[0]	values[1]	values[4]	230	1			T69	13		T221	60		T238	14
auto[0]	values[1]	values[5]	148	1			T34	15		T79	12		T239	2
auto[0]	values[1]	values[6]	404	1			T166	16		T221	42		T208	12
auto[0]	values[1]	values[7]	173	1			T240	2		T172	9		T34	9
auto[0]	values[2]	values[0]	238	1			T74	14		T29	10		T30	14
auto[0]	values[2]	values[1]	150	1			T170	12		T79	28		T241	14
auto[0]	values[2]	values[2]	263	1			T9	11		T169	20		T172	13
auto[0]	values[2]	values[3]	203	1			T86	18		T34	13		T35	14
auto[0]	values[2]	values[4]	190	1			T31	22		T242	6		T170	13
auto[0]	values[2]	values[5]	264	1			T26	14		T31	12		T243	18
auto[0]	values[2]	values[6]	156	1			T25	14		T32	13		T34	6
auto[0]	values[2]	values[7]	119	1			T192	38		T244	13		T189	11
auto[0]	values[3]	values[0]	86	1			T35	12		T196	10		T208	12
auto[0]	values[3]	values[1]	458	1			T245	8		T209	14		T246	10
auto[0]	values[3]	values[2]	175	1			T233	4		T33	11		T215	2
auto[0]	values[3]	values[3]	220	1			T26	13		T31	10		T166	11
auto[0]	values[3]	values[4]	178	1			T247	4		T35	15		T248	4
auto[0]	values[3]	values[5]	206	1			T26	17		T194	10		T34	13
auto[0]	values[3]	values[6]	291	1			T9	16		T213	6		T79	19
auto[0]	values[3]	values[7]	202	1			T35	8		T249	36		T250	33
auto[0]	values[4]	values[0]	193	1			T170	9		T192	12		T221	11
auto[0]	values[4]	values[1]	168	1			T172	11		T251	6		T252	6
auto[0]	values[4]	values[2]	254	1			T26	8		T34	81		T152	51
auto[0]	values[4]	values[3]	163	1			T9	6		T31	8		T192	24
auto[0]	values[4]	values[4]	266	1			T31	10		T32	11		T194	12
auto[0]	values[4]	values[5]	122	1			T34	11		T79	9		T253	10
auto[0]	values[4]	values[6]	217	1			T25	8		T190	6		T32	12
auto[0]	values[4]	values[7]	106	1			T13	2		T254	9		T150	18
auto[0]	values[5]	values[0]	156	1			T9	4		T26	7		T197	2
auto[0]	values[5]	values[1]	339	1			T9	10		T31	28		T33	10
auto[0]	values[5]	values[2]	164	1			T30	11		T170	24		T167	12
auto[0]	values[5]	values[3]	303	1			T31	10		T33	9		T192	30
auto[0]	values[5]	values[4]	246	1			T31	14		T192	10		T20	26
auto[0]	values[5]	values[5]	181	1			T26	12		T255	17		T244	15
auto[0]	values[5]	values[6]	182	1			T25	14		T29	8		T33	14
auto[0]	values[5]	values[7]	176	1			T9	23		T32	10		T33	10
auto[0]	values[6]	values[0]	109	1			T20	29		T196	11		T221	17
auto[0]	values[6]	values[1]	134	1			T25	10		T29	6		T256	2
auto[0]	values[6]	values[2]	244	1			T27	6		T35	36		T69	10
auto[0]	values[6]	values[3]	131	1			T171	50		T34	12		T221	6
auto[0]	values[6]	values[4]	312	1			T10	18		T28	16		T29	8
auto[0]	values[6]	values[5]	227	1			T25	12		T29	16		T30	12
auto[0]	values[6]	values[6]	248	1			T26	12		T192	15		T257	4
auto[0]	values[6]	values[7]	131	1			T258	8		T259	35		T260	12
auto[0]	values[7]	values[0]	197	1			T36	2		T25	13		T31	9
auto[0]	values[7]	values[1]	145	1			T196	11		T261	10		T132	21
auto[0]	values[7]	values[2]	217	1			T32	13		T79	23		T262	6
auto[0]	values[7]	values[3]	209	1			T9	13		T32	37		T33	18
auto[0]	values[7]	values[4]	240	1			T9	7		T168	14		T254	14
auto[0]	values[7]	values[5]	259	1			T26	17		T170	10		T79	38
auto[0]	values[7]	values[6]	218	1			T231	4		T31	7		T32	9
auto[0]	values[7]	values[7]	192	1			T32	10		T170	50		T125	12
auto[1]	values[0]	values[0]	180	1			T9	71		T33	9		T204	11
auto[1]	values[0]	values[1]	86	1			T26	20		T29	12		T31	3
auto[1]	values[0]	values[2]	99	1			T25	5		T29	9		T198	12
auto[1]	values[0]	values[3]	105	1			T32	9		T199	11		T189	13
auto[1]	values[0]	values[4]	249	1			T32	17		T167	14		T69	6
auto[1]	values[0]	values[5]	100	1			T29	21		T30	12		T34	13
auto[1]	values[0]	values[6]	117	1			T31	14		T234	3		T196	8
auto[1]	values[0]	values[7]	116	1			T25	14		T20	7		T221	12
auto[1]	values[1]	values[0]	186	1			T25	18		T29	10		T194	5
auto[1]	values[1]	values[1]	100	1			T33	7		T170	10		T263	4
auto[1]	values[1]	values[2]	121	1			T9	6		T188	18		T237	13
auto[1]	values[1]	values[3]	93	1			T264	18		T204	7		T265	7
auto[1]	values[1]	values[4]	80	1			T69	9		T221	8		T238	6
auto[1]	values[1]	values[5]	213	1			T200	10		T34	5		T79	8
auto[1]	values[1]	values[6]	129	1			T166	5		T221	21		T208	8
auto[1]	values[1]	values[7]	126	1			T172	11		T34	11		T35	33
auto[1]	values[2]	values[0]	157	1			T29	10		T30	6		T201	16
auto[1]	values[2]	values[1]	121	1			T170	8		T79	18		T20	22
auto[1]	values[2]	values[2]	155	1			T9	9		T172	7		T192	10
auto[1]	values[2]	values[3]	152	1			T34	7		T35	6		T196	11
auto[1]	values[2]	values[4]	120	1			T31	9		T170	7		T192	22
auto[1]	values[2]	values[5]	245	1			T26	11		T31	9		T170	25
auto[1]	values[2]	values[6]	287	1			T25	13		T32	7		T34	14
auto[1]	values[2]	values[7]	176	1			T266	10		T192	9		T244	7
auto[1]	values[3]	values[0]	128	1			T35	8		T196	11		T208	66
auto[1]	values[3]	values[1]	122	1			T35	9		T79	9		T196	12
auto[1]	values[3]	values[2]	116	1			T33	9		T170	11		T167	9
auto[1]	values[3]	values[3]	159	1			T26	7		T31	15		T166	10
auto[1]	values[3]	values[4]	130	1			T35	5		T196	12		T81	3
auto[1]	values[3]	values[5]	179	1			T26	8		T194	10		T34	7
auto[1]	values[3]	values[6]	193	1			T9	13		T79	7		T221	7
auto[1]	values[3]	values[7]	72	1			T35	12		T267	16		T217	6
auto[1]	values[4]	values[0]	222	1			T170	13		T192	27		T221	9
auto[1]	values[4]	values[1]	168	1			T172	12		T167	12		T254	12
auto[1]	values[4]	values[2]	99	1			T26	12		T34	6		T268	16
auto[1]	values[4]	values[3]	277	1			T9	14		T31	14		T192	4
auto[1]	values[4]	values[4]	231	1			T31	10		T32	9		T194	11
auto[1]	values[4]	values[5]	176	1			T34	42		T79	11		T150	25
auto[1]	values[4]	values[6]	181	1			T25	21		T32	8		T34	10
auto[1]	values[4]	values[7]	102	1			T254	11		T150	8		T217	11
auto[1]	values[5]	values[0]	127	1			T9	16		T26	13		T35	8
auto[1]	values[5]	values[1]	248	1			T9	21		T31	19		T33	10
auto[1]	values[5]	values[2]	271	1			T30	30		T170	19		T167	9
auto[1]	values[5]	values[3]	207	1			T31	10		T33	12		T192	9
auto[1]	values[5]	values[4]	176	1			T31	11		T192	10		T20	26
auto[1]	values[5]	values[5]	94	1			T26	8		T244	5		T152	9
auto[1]	values[5]	values[6]	234	1			T25	12		T29	12		T33	7
auto[1]	values[5]	values[7]	135	1			T9	17		T32	10		T33	11
auto[1]	values[6]	values[0]	92	1			T20	20		T196	12		T221	27
auto[1]	values[6]	values[1]	126	1			T25	10		T29	19		T150	11
auto[1]	values[6]	values[2]	138	1			T35	17		T69	10		T244	10
auto[1]	values[6]	values[3]	75	1			T34	8		T221	14		T265	14
auto[1]	values[6]	values[4]	255	1			T29	14		T35	7		T170	67
auto[1]	values[6]	values[5]	105	1			T25	12		T29	4		T30	8
auto[1]	values[6]	values[6]	187	1			T26	11		T192	5		T204	11
auto[1]	values[6]	values[7]	48	1			T260	8		T269	28		T270	12
auto[1]	values[7]	values[0]	193	1			T25	7		T31	11		T58	8
auto[1]	values[7]	values[1]	160	1			T196	9		T261	10		T271	4
auto[1]	values[7]	values[2]	150	1			T32	7		T79	22		T272	8
auto[1]	values[7]	values[3]	95	1			T9	17		T32	6		T33	6
auto[1]	values[7]	values[4]	126	1			T9	13		T254	6		T204	6
auto[1]	values[7]	values[5]	113	1			T26	3		T170	10		T79	12
auto[1]	values[7]	values[6]	310	1			T31	13		T32	27		T170	6
auto[1]	values[7]	values[7]	122	1			T32	31		T170	19		T273	6