Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	320	1			T2	4		T9	4		T25	1
auto[ReadAddrCrossIntoMailbox]	241	1			T9	2		T26	1		T29	1
auto[ReadAddrCrossOutOfMailbox]	261	1			T9	2		T29	1		T30	1
auto[ReadAddrCrossAllMailbox]	177	1			T26	2		T29	4		T31	1
auto[ReadAddrOutsideMailbox]	2692	1			T2	4		T9	35		T24	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1857

1

T2

4

T9

19

T24

1

auto[1]

1834

1

T2

4

T9

24

T24

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	610	1			T9	7		T74	2		T25	4
read_ops[0x0b]	615	1			T9	5		T24	2		T36	2
read_ops[0x3b]	634	1			T2	4		T9	7		T25	8
read_ops[0x6b]	622	1			T2	2		T9	8		T74	2
read_ops[0xbb]	590	1			T9	10		T25	7		T26	6
read_ops[0xeb]	620	1			T2	2		T9	6		T25	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T9	1		T32	1		T209	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T29	1		T33	1		T34	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T31	3		T203	1		T170	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T9	1		T203	1		T35	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T31	1		T32	1		T33	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T32	1		T34	3		T35	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T172	1		T204	1		T244	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T35	1		T196	1		T21	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T9	4		T74	1		T25	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	216	1			T9	1		T74	1		T25	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T198	1		T32	2		T172	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T9	1		T34	1		T211	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T32	2		T210	2		T157	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T170	2		T210	2		T157	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T31	1		T170	1		T210	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T35	1		T210	1		T274	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T29	2		T172	1		T170	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T31	1		T34	1		T210	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	209	1			T9	3		T24	1		T36	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	238	1			T9	1		T24	1		T36	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T25	1		T34	1		T35	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T9	1		T29	2		T20	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T26	1		T32	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T30	2		T31	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T198	1		T34	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T32	1		T20	1		T219	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T172	1		T244	1		T196	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T35	1		T192	1		T69	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	233	1			T2	2		T9	1		T25	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	226	1			T2	2		T9	5		T25	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T2	1		T31	1		T79	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T2	1		T31	1		T32	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T31	2		T198	1		T32	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T35	1		T219	1		T204	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T29	1		T34	1		T35	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	14	1			T219	2		T254	1		T238	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T35	2		T210	1		T192	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T26	1		T35	1		T210	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	228	1			T9	2		T74	1		T25	8
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	241	1			T9	6		T74	1		T25	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T30	1		T31	1		T157	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T34	1		T170	1		T157	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T29	1		T31	1		T166	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T9	1		T32	1		T34	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T9	2		T30	1		T35	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T32	1		T34	1		T35	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T26	1		T29	1		T225	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T192	1		T274	1		T199	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	221	1			T9	4		T25	5		T26	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	196	1			T9	3		T25	2		T26	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T2	1		T34	1		T211	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T2	1		T9	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T31	2		T33	1		T34	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T34	1		T170	1		T79	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T244	1		T150	1		T275	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T35	1		T166	1		T170	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T32	1		T20	1		T189	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T29	1		T192	1		T20	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	195	1			T9	2		T29	3		T30	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	244	1			T9	3		T25	2		T26	5