Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2621598	1			T1	4097		T2	1		T3	899
all_pins[1]	2621598	1			T1	4097		T2	1		T3	899
all_pins[2]	2621598	1			T1	4097		T2	1		T3	899
all_pins[3]	2621598	1			T1	4097		T2	1		T3	899
all_pins[4]	2621598	1			T1	4097		T2	1		T3	899
all_pins[5]	2621598	1			T1	4097		T2	1		T3	899
all_pins[6]	2621598	1			T1	4097		T2	1		T3	899
all_pins[7]	2621598	1			T1	4097		T2	1		T3	899

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20901853	1			T1	32776		T2	8		T3	7192
values[0x1]	70931	1			T37	162		T54	26		T32	7
transitions[0x0=>0x1]	68140	1			T37	160		T54	17		T32	5
transitions[0x1=>0x0]	68157	1			T37	160		T54	17		T32	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2621253	1			T1	4097		T2	1		T3	899
all_pins[0]	values[0x1]	345	1			T54	5		T33	9		T58	1
all_pins[0]	transitions[0x0=>0x1]	262	1			T54	3		T33	8		T58	1
all_pins[0]	transitions[0x1=>0x0]	421	1			T37	157		T54	2		T32	2
all_pins[1]	values[0x0]	2621094	1			T1	4097		T2	1		T3	899
all_pins[1]	values[0x1]	504	1			T37	157		T54	4		T32	2
all_pins[1]	transitions[0x0=>0x1]	439	1			T37	156		T54	3		T33	5
all_pins[1]	transitions[0x1=>0x0]	137	1			T54	3		T33	2		T58	2
all_pins[2]	values[0x0]	2621396	1			T1	4097		T2	1		T3	899
all_pins[2]	values[0x1]	202	1			T37	1		T54	4		T32	2
all_pins[2]	transitions[0x0=>0x1]	169	1			T54	3		T32	2		T33	2
all_pins[2]	transitions[0x1=>0x0]	152	1			T32	1		T33	3		T166	3
all_pins[3]	values[0x0]	2621413	1			T1	4097		T2	1		T3	899
all_pins[3]	values[0x1]	185	1			T37	1		T54	1		T32	1
all_pins[3]	transitions[0x0=>0x1]	137	1			T37	1		T54	1		T32	1
all_pins[3]	transitions[0x1=>0x0]	124	1			T37	1		T54	2		T33	4
all_pins[4]	values[0x0]	2621426	1			T1	4097		T2	1		T3	899
all_pins[4]	values[0x1]	172	1			T37	1		T54	2		T33	4
all_pins[4]	transitions[0x0=>0x1]	129	1			T37	1		T54	1		T33	4
all_pins[4]	transitions[0x1=>0x0]	3525	1			T54	4		T33	3		T58	447
all_pins[5]	values[0x0]	2618030	1			T1	4097		T2	1		T3	899
all_pins[5]	values[0x1]	3568	1			T54	5		T33	3		T58	447
all_pins[5]	transitions[0x0=>0x1]	1156	1			T54	4		T33	3		T58	447
all_pins[5]	transitions[0x1=>0x0]	63364	1			T54	2		T32	2		T33	1
all_pins[6]	values[0x0]	2555822	1			T1	4097		T2	1		T3	899
all_pins[6]	values[0x1]	65776	1			T54	3		T32	2		T33	1
all_pins[6]	transitions[0x0=>0x1]	65725	1			T54	1		T32	2		T33	1
all_pins[6]	transitions[0x1=>0x0]	128	1			T37	2		T33	3		T58	2
all_pins[7]	values[0x0]	2621419	1			T1	4097		T2	1		T3	899
all_pins[7]	values[0x1]	179	1			T37	2		T54	2		T33	3
all_pins[7]	transitions[0x0=>0x1]	123	1			T37	2		T54	1		T33	1
all_pins[7]	transitions[0x1=>0x0]	306	1			T54	4		T33	7		T58	1