Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2728	1			T9	20		T25	24		T26	25
values[1]	3109	1			T2	10		T9	137		T25	46
values[2]	2784	1			T25	32		T26	20		T197	2
values[3]	2885	1			T9	20		T13	2		T24	14
values[4]	3522	1			T9	50		T25	29		T26	23
values[5]	2412	1			T74	14		T25	20		T92	14
values[6]	2658	1			T9	20		T10	18		T26	45
values[7]	2899	1			T9	130		T25	27		T29	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2654	1			T9	60		T74	14		T28	16
values[1]	2788	1			T10	18		T25	20		T26	20
values[2]	2651	1			T9	40		T25	44		T92	14
values[3]	2974	1			T2	10		T9	90		T26	20
values[4]	2673	1			T9	70		T26	48		T190	6
values[5]	2710	1			T9	20		T24	14		T88	2
values[6]	3390	1			T9	77		T25	55		T26	25
values[7]	3157	1			T9	20		T13	2		T36	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22647

1

T2

10

T9

374

T10

18

auto[1]

350

1

T9

3

T25

5

T26

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	404	1			T231	4		T31	23		T198	25
auto[0]	values[0]	values[1]	241	1			T31	20		T58	20		T266	10
auto[0]	values[0]	values[2]	375	1			T25	23		T194	23		T35	33
auto[0]	values[0]	values[3]	239	1			T242	6		T209	14		T268	16
auto[0]	values[0]	values[4]	286	1			T26	25		T276	6		T79	26
auto[0]	values[0]	values[5]	361	1			T9	20		T79	23		T199	21
auto[0]	values[0]	values[6]	388	1			T32	20		T35	39		T170	38
auto[0]	values[0]	values[7]	401	1			T29	28		T32	20		T194	47
auto[0]	values[1]	values[0]	271	1			T9	59		T26	23		T34	20
auto[0]	values[1]	values[1]	404	1			T25	20		T170	20		T79	63
auto[0]	values[1]	values[2]	366	1			T192	37		T204	20		T267	50
auto[0]	values[1]	values[3]	190	1			T2	10		T167	22		T69	22
auto[0]	values[1]	values[4]	588	1			T32	44		T277	12		T128	24
auto[0]	values[1]	values[5]	438	1			T34	107		T157	14		T20	21
auto[0]	values[1]	values[6]	458	1			T9	76		T29	20		T169	20
auto[0]	values[1]	values[7]	343	1			T25	26		T32	36		T33	22
auto[0]	values[2]	values[0]	241	1			T35	20		T210	12		T167	20
auto[0]	values[2]	values[1]	356	1			T34	18		T20	23		T254	19
auto[0]	values[2]	values[2]	351	1			T31	22		T278	14		T279	34
auto[0]	values[2]	values[3]	379	1			T26	20		T197	2		T170	75
auto[0]	values[2]	values[4]	301	1			T79	26		T208	35		T152	27
auto[0]	values[2]	values[5]	193	1			T33	21		T150	20		T221	20
auto[0]	values[2]	values[6]	529	1			T32	43		T33	20		T215	2
auto[0]	values[2]	values[7]	391	1			T25	30		T32	20		T246	10
auto[0]	values[3]	values[0]	322	1			T28	16		T170	21		T159	20
auto[0]	values[3]	values[1]	363	1			T34	44		T280	20		T208	79
auto[0]	values[3]	values[2]	363	1			T9	20		T25	20		T26	20
auto[0]	values[3]	values[3]	406	1			T29	19		T170	20		T272	8
auto[0]	values[3]	values[4]	299	1			T33	20		T35	20		T79	20
auto[0]	values[3]	values[5]	356	1			T24	14		T31	27		T32	20
auto[0]	values[3]	values[6]	352	1			T25	28		T29	25		T281	8
auto[0]	values[3]	values[7]	376	1			T13	2		T36	2		T31	23
auto[0]	values[4]	values[0]	550	1			T29	20		T30	20		T31	20
auto[0]	values[4]	values[1]	382	1			T34	17		T244	29		T273	20
auto[0]	values[4]	values[2]	388	1			T29	22		T170	22		T167	21
auto[0]	values[4]	values[3]	534	1			T31	20		T172	20		T34	66
auto[0]	values[4]	values[4]	290	1			T9	50		T26	23		T32	22
auto[0]	values[4]	values[5]	431	1			T32	18		T35	20		T192	20
auto[0]	values[4]	values[6]	367	1			T196	43		T282	2		T283	2
auto[0]	values[4]	values[7]	528	1			T25	28		T29	22		T240	2
auto[0]	values[5]	values[0]	354	1			T74	14		T25	20		T26	20
auto[0]	values[5]	values[1]	445	1			T35	20		T170	46		T258	8
auto[0]	values[5]	values[2]	206	1			T92	14		T31	20		T167	19
auto[0]	values[5]	values[3]	319	1			T30	19		T203	4		T69	20
auto[0]	values[5]	values[4]	213	1			T190	6		T245	8		T211	10
auto[0]	values[5]	values[5]	310	1			T88	2		T26	20		T233	4
auto[0]	values[5]	values[6]	251	1			T29	20		T20	21		T219	16
auto[0]	values[5]	values[7]	279	1			T26	23		T34	35		T35	20
auto[0]	values[6]	values[0]	136	1			T194	20		T220	2		T284	12
auto[0]	values[6]	values[1]	302	1			T10	18		T26	20		T31	31
auto[0]	values[6]	values[2]	288	1			T170	24		T167	23		T285	4
auto[0]	values[6]	values[3]	401	1			T168	14		T263	4		T218	24
auto[0]	values[6]	values[4]	451	1			T166	21		T79	24		T192	95
auto[0]	values[6]	values[5]	289	1			T200	10		T243	18		T167	21
auto[0]	values[6]	values[6]	423	1			T26	25		T171	50		T235	2
auto[0]	values[6]	values[7]	331	1			T9	20		T31	40		T86	18
auto[0]	values[7]	values[0]	334	1			T264	18		T20	28		T123	96
auto[0]	values[7]	values[1]	233	1			T27	6		T31	17		T32	20
auto[0]	values[7]	values[2]	277	1			T9	20		T34	20		T35	42
auto[0]	values[7]	values[3]	463	1			T9	89		T213	6		T164	10
auto[0]	values[7]	values[4]	214	1			T9	20		T35	20		T69	21
auto[0]	values[7]	values[5]	294	1			T30	20		T35	18		T189	25
auto[0]	values[7]	values[6]	585	1			T25	26		T29	20		T31	25
auto[0]	values[7]	values[7]	448	1			T35	48		T236	4		T212	12
auto[1]	values[0]	values[0]	2	1			T31	2		-	-		-	-
auto[1]	values[0]	values[1]	4	1			T31	1		T192	1		T286	1
auto[1]	values[0]	values[2]	3	1			T25	1		T221	1		T287	1
auto[1]	values[0]	values[3]	3	1			T196	1		T133	2		-	-
auto[1]	values[0]	values[4]	3	1			T288	2		T289	1		-	-
auto[1]	values[0]	values[5]	7	1			T150	2		T267	3		T290	2
auto[1]	values[0]	values[6]	5	1			T192	2		T132	1		T134	2
auto[1]	values[0]	values[7]	6	1			T29	2		T269	1		T290	3
auto[1]	values[1]	values[0]	7	1			T9	1		T170	1		T20	2
auto[1]	values[1]	values[1]	11	1			T79	2		T217	2		T133	3
auto[1]	values[1]	values[2]	7	1			T192	2		T267	1		T134	3
auto[1]	values[1]	values[3]	2	1			T191	1		T291	1		-	-
auto[1]	values[1]	values[4]	4	1			T32	1		T191	3		-	-
auto[1]	values[1]	values[5]	4	1			T152	3		T269	1		-	-
auto[1]	values[1]	values[6]	8	1			T9	1		T170	1		T292	4
auto[1]	values[1]	values[7]	8	1			T33	2		T69	1		T196	1
auto[1]	values[2]	values[0]	8	1			T221	1		T133	2		T293	3
auto[1]	values[2]	values[1]	9	1			T34	2		T20	1		T254	1
auto[1]	values[2]	values[2]	6	1			T189	1		T191	2		T294	2
auto[1]	values[2]	values[3]	4	1			T150	2		T221	1		T295	1
auto[1]	values[2]	values[4]	2	1			T296	2		-	-		-	-
auto[1]	values[2]	values[5]	2	1			T150	1		T296	1		-	-
auto[1]	values[2]	values[6]	5	1			T260	1		T297	2		T217	1
auto[1]	values[2]	values[7]	7	1			T25	2		T165	2		T192	1
auto[1]	values[3]	values[0]	3	1			T170	2		T152	1		-	-
auto[1]	values[3]	values[1]	7	1			T34	1		T208	2		T298	2
auto[1]	values[3]	values[2]	7	1			T275	1		T189	1		T134	5
auto[1]	values[3]	values[3]	7	1			T29	1		T299	2		T300	1
auto[1]	values[3]	values[4]	9	1			T33	1		T163	4		T301	2
auto[1]	values[3]	values[5]	4	1			T295	2		T302	2		-	-
auto[1]	values[3]	values[6]	3	1			T303	1		T134	2		-	-
auto[1]	values[3]	values[7]	8	1			T31	2		T34	1		T132	1
auto[1]	values[4]	values[0]	9	1			T166	1		T208	2		T195	1
auto[1]	values[4]	values[1]	12	1			T34	3		T299	2		T191	3
auto[1]	values[4]	values[2]	4	1			T189	1		T296	2		T304	1
auto[1]	values[4]	values[3]	9	1			T150	2		T81	1		T260	3
auto[1]	values[4]	values[4]	5	1			T32	1		T295	4		-	-
auto[1]	values[4]	values[5]	4	1			T32	2		T288	2		-	-
auto[1]	values[4]	values[6]	2	1			T305	1		T270	1		-	-
auto[1]	values[4]	values[7]	7	1			T25	1		T34	1		T192	1
auto[1]	values[5]	values[0]	1	1			T291	1		-	-		-	-
auto[1]	values[5]	values[1]	8	1			T170	4		T297	2		T306	2
auto[1]	values[5]	values[2]	3	1			T167	1		T288	2		-	-
auto[1]	values[5]	values[3]	5	1			T30	1		T195	1		T269	3
auto[1]	values[5]	values[4]	4	1			T166	3		T291	1		-	-
auto[1]	values[5]	values[5]	7	1			T208	2		T301	2		T307	2
auto[1]	values[5]	values[6]	3	1			T20	1		T293	1		T269	1
auto[1]	values[5]	values[7]	4	1			T26	2		T20	1		T260	1
auto[1]	values[6]	values[0]	2	1			T303	1		T191	1		-	-
auto[1]	values[6]	values[1]	3	1			T234	2		T287	1		-	-
auto[1]	values[6]	values[2]	3	1			T308	2		T305	1		-	-
auto[1]	values[6]	values[3]	5	1			T218	2		T304	3		-	-
auto[1]	values[6]	values[4]	3	1			T237	2		T295	1		-	-
auto[1]	values[6]	values[5]	3	1			T167	1		T20	2		-	-
auto[1]	values[6]	values[6]	6	1			T172	1		T170	1		T150	1
auto[1]	values[6]	values[7]	12	1			T221	1		T81	1		T299	1
auto[1]	values[7]	values[0]	10	1			T309	2		T132	5		T310	1
auto[1]	values[7]	values[1]	8	1			T31	3		T150	1		T21	1
auto[1]	values[7]	values[2]	4	1			T35	1		T307	1		T311	2
auto[1]	values[7]	values[3]	8	1			T9	1		T164	4		T221	1
auto[1]	values[7]	values[4]	1	1			T69	1		-	-		-	-
auto[1]	values[7]	values[5]	7	1			T35	2		T307	2		T306	1
auto[1]	values[7]	values[6]	5	1			T25	1		T31	2		T221	1
auto[1]	values[7]	values[7]	8	1			T35	1		T293	3		T308	1