Summary for Variable cp_addr_4b_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_addr_4b_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1188 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
5 |
auto[1] |
1241 |
1 |
|
|
T1 |
4 |
|
T4 |
7 |
|
T9 |
6 |
Summary for Variable cp_prev_addr_4b_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_prev_addr_4b_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1191 |
1 |
|
|
T1 |
2 |
|
T3 |
4 |
|
T4 |
6 |
auto[1] |
1238 |
1 |
|
|
T1 |
3 |
|
T4 |
6 |
|
T9 |
7 |
Summary for Cross cr_all
Samples crossed: cp_addr_4b_en cp_prev_addr_4b_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_addr_4b_en | cp_prev_addr_4b_en | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
624 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T4 |
3 |
auto[0] |
auto[1] |
564 |
1 |
|
|
T4 |
2 |
|
T9 |
4 |
|
T13 |
1 |
auto[1] |
auto[0] |
567 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T9 |
3 |
auto[1] |
auto[1] |
674 |
1 |
|
|
T1 |
3 |
|
T4 |
4 |
|
T9 |
3 |