Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1895

1

T1

3

T6

7

T7

2

auto[1]

1901

1

T1

5

T6

5

T7

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2130

1

T1

5

T6

12

T9

19

auto[1]

1666

1

T1

3

T7

3

T9

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2949

1

T1

7

T6

5

T7

3

auto[1]

847

1

T1

1

T6

7

T9

12

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	777	1			T1	1		T6	3		T9	6
valid[1]	755	1			T1	1		T6	1		T9	5
valid[2]	746	1			T1	2		T6	4		T7	1
valid[3]	757	1			T1	1		T6	2		T7	1
valid[4]	761	1			T1	3		T6	2		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	110	1			T9	1		T16	2		T17	1
auto[0]	auto[0]	valid[0]	auto[1]	175	1			T84	1		T85	2		T335	1
auto[0]	auto[0]	valid[1]	auto[0]	130	1			T6	1		T9	1		T14	1
auto[0]	auto[0]	valid[1]	auto[1]	192	1			T1	1		T14	1		T82	1
auto[0]	auto[0]	valid[2]	auto[0]	134	1			T14	1		T16	4		T37	1
auto[0]	auto[0]	valid[2]	auto[1]	142	1			T18	1		T84	1		T335	3
auto[0]	auto[0]	valid[3]	auto[0]	130	1			T6	1		T14	1		T16	1
auto[0]	auto[0]	valid[3]	auto[1]	163	1			T7	1		T9	1		T18	2
auto[0]	auto[0]	valid[4]	auto[0]	148	1			T1	1		T6	2		T9	1
auto[0]	auto[0]	valid[4]	auto[1]	149	1			T7	1		T14	1		T335	1
auto[0]	auto[1]	valid[0]	auto[0]	163	1			T1	1		T6	1		T9	1
auto[0]	auto[1]	valid[0]	auto[1]	153	1			T18	1		T82	1		T83	1
auto[0]	auto[1]	valid[1]	auto[0]	124	1			T9	2		T14	1		T16	1
auto[0]	auto[1]	valid[1]	auto[1]	161	1			T9	1		T14	1		T84	3
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T1	1		T16	1		T25	1
auto[0]	auto[1]	valid[2]	auto[1]	170	1			T1	1		T7	1		T14	1
auto[0]	auto[1]	valid[3]	auto[0]	118	1			T1	1		T9	1		T16	1
auto[0]	auto[1]	valid[3]	auto[1]	159	1			T84	1		T335	1		T33	3
auto[0]	auto[1]	valid[4]	auto[0]	102	1			T23	1		T25	1		T37	2
auto[0]	auto[1]	valid[4]	auto[1]	202	1			T1	1		T18	2		T84	2
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T6	1		T9	1		T14	1
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T9	1		T16	1		T39	1
auto[1]	auto[0]	valid[2]	auto[0]	84	1			T6	1		T9	1		T14	1
auto[1]	auto[0]	valid[3]	auto[0]	99	1			T6	1		T14	1		T39	1
auto[1]	auto[0]	valid[4]	auto[0]	79	1			T1	1		T9	3		T25	2
auto[1]	auto[1]	valid[0]	auto[0]	94	1			T6	1		T9	3		T14	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T14	4		T25	1		T82	1
auto[1]	auto[1]	valid[2]	auto[0]	92	1			T6	3		T9	2		T26	1
auto[1]	auto[1]	valid[3]	auto[0]	88	1			T14	1		T16	1		T37	1
auto[1]	auto[1]	valid[4]	auto[0]	81	1			T9	1		T14	1		T16	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal