Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53296

1

T1

258

T6

270

T9

369

auto[1]

17473

1

T1

37

T7

3

T9

51

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51224

1

T1

191

T6

171

T7

3

auto[1]

19545

1

T1

104

T6

99

T9

134

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36855	1			T1	160		T6	133		T7	3
others[1]	5683	1			T1	19		T6	24		T9	30
others[2]	5967	1			T1	32		T6	22		T9	43
others[3]	6666	1			T1	21		T6	30		T9	37
interest[1]	3886	1			T1	11		T6	19		T9	20
interest[4]	24222	1			T1	106		T6	85		T7	3
interest[64]	11712	1			T1	52		T6	42		T9	70

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17419	1			T1	87		T6	83		T9	126
auto[0]	auto[0]	others[1]	2791	1			T1	5		T6	14		T9	21
auto[0]	auto[0]	others[2]	2837	1			T1	15		T6	13		T9	25
auto[0]	auto[0]	others[3]	3185	1			T1	12		T6	19		T9	17
auto[0]	auto[0]	interest[1]	1893	1			T1	5		T6	14		T9	12
auto[0]	auto[0]	interest[4]	11461	1			T1	66		T6	49		T9	94
auto[0]	auto[0]	interest[64]	5626	1			T1	30		T6	28		T9	34
auto[0]	auto[1]	others[0]	9266	1			T1	20		T7	3		T9	25
auto[0]	auto[1]	others[1]	1342	1			T1	5		T9	1		T14	5
auto[0]	auto[1]	others[2]	1460	1			T1	3		T9	4		T14	3
auto[0]	auto[1]	others[3]	1616	1			T1	3		T9	6		T14	2
auto[0]	auto[1]	interest[1]	919	1			T1	2		T9	1		T14	5
auto[0]	auto[1]	interest[4]	6200	1			T1	12		T7	3		T9	15
auto[0]	auto[1]	interest[64]	2870	1			T1	4		T9	14		T14	9
auto[1]	auto[0]	others[0]	10170	1			T1	53		T6	50		T9	69
auto[1]	auto[0]	others[1]	1550	1			T1	9		T6	10		T9	8
auto[1]	auto[0]	others[2]	1670	1			T1	14		T6	9		T9	14
auto[1]	auto[0]	others[3]	1865	1			T1	6		T6	11		T9	14
auto[1]	auto[0]	interest[1]	1074	1			T1	4		T6	5		T9	7
auto[1]	auto[0]	interest[4]	6561	1			T1	28		T6	36		T9	43
auto[1]	auto[0]	interest[64]	3216	1			T1	18		T6	14		T9	22

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal