Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	760	1			T37	7		T54	11		T32	4
all_values[1]	760	1			T37	7		T54	11		T32	4
all_values[2]	760	1			T37	7		T54	11		T32	4
all_values[3]	760	1			T37	7		T54	11		T32	4
all_values[4]	760	1			T37	7		T54	11		T32	4
all_values[5]	760	1			T37	7		T54	11		T32	4
all_values[6]	760	1			T37	7		T54	11		T32	4
all_values[7]	760	1			T37	7		T54	11		T32	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3266

1

T37

24

T54

42

T32

18

auto[1]

2814

1

T37

32

T54

46

T32

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2431

1

T37

26

T54

34

T32

15

auto[1]

3649

1

T37

30

T54

54

T32

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3453

1

T37

30

T54

51

T32

20

auto[1]

2627

1

T37

26

T54

37

T32

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	157	1			T37	1		T54	1		T32	2
all_values[0]	auto[0]	auto[0]	auto[1]	79	1			T37	1		T54	2		T33	2
all_values[0]	auto[0]	auto[1]	auto[0]	127	1			T37	2		T33	2		T58	1
all_values[0]	auto[0]	auto[1]	auto[1]	74	1			T54	3		T33	3		T58	1
all_values[0]	auto[1]	auto[0]	auto[1]	175	1			T37	2		T54	3		T32	2
all_values[0]	auto[1]	auto[1]	auto[1]	148	1			T37	1		T54	2		T33	5
all_values[1]	auto[0]	auto[0]	auto[0]	148	1			T54	3		T32	1		T33	1
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T33	2		T58	1		T149	1
all_values[1]	auto[0]	auto[1]	auto[0]	129	1			T37	2		T54	2		T166	2
all_values[1]	auto[0]	auto[1]	auto[1]	61	1			T54	3		T32	1		T33	2
all_values[1]	auto[1]	auto[0]	auto[1]	198	1			T54	1		T33	5		T58	5
all_values[1]	auto[1]	auto[1]	auto[1]	146	1			T37	5		T54	2		T32	2
all_values[2]	auto[0]	auto[0]	auto[0]	170	1			T37	1		T54	4		T32	1
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T37	1		T33	2		T58	1
all_values[2]	auto[0]	auto[1]	auto[0]	114	1			T37	2		T32	1		T33	2
all_values[2]	auto[0]	auto[1]	auto[1]	56	1			T54	2		T32	1		T33	1
all_values[2]	auto[1]	auto[0]	auto[1]	180	1			T37	1		T54	1		T33	5
all_values[2]	auto[1]	auto[1]	auto[1]	158	1			T37	2		T54	4		T32	1
all_values[3]	auto[0]	auto[0]	auto[0]	135	1			T54	1		T32	2		T33	2
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T33	2		T166	1		T167	2
all_values[3]	auto[0]	auto[1]	auto[0]	133	1			T37	2		T54	5		T33	2
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T37	1		T54	1		T32	1
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T37	1		T54	2		T32	1
all_values[3]	auto[1]	auto[1]	auto[1]	160	1			T37	3		T54	2		T33	2
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T37	2		T54	3		T32	1
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T54	2		T33	1		T79	1
all_values[4]	auto[0]	auto[1]	auto[0]	153	1			T37	2		T54	1		T32	2
all_values[4]	auto[0]	auto[1]	auto[1]	67	1			T33	2		T80	1		T149	3
all_values[4]	auto[1]	auto[0]	auto[1]	162	1			T54	3		T33	2		T58	3
all_values[4]	auto[1]	auto[1]	auto[1]	145	1			T37	3		T54	2		T32	1
all_values[5]	auto[0]	auto[0]	auto[0]	201	1			T37	7		T32	1		T33	4
all_values[5]	auto[0]	auto[1]	auto[0]	222	1			T54	3		T32	2		T33	5
all_values[5]	auto[1]	auto[0]	auto[1]	169	1			T54	3		T32	1		T33	1
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T54	5		T33	4		T58	1
all_values[6]	auto[0]	auto[0]	auto[0]	177	1			T37	3		T54	3		T32	1
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T54	1		T33	3		T79	1
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T37	1		T54	2		T33	4
all_values[6]	auto[0]	auto[1]	auto[1]	64	1			T54	1		T32	1		T166	2
all_values[6]	auto[1]	auto[0]	auto[1]	176	1			T37	2		T54	3		T32	1
all_values[6]	auto[1]	auto[1]	auto[1]	143	1			T37	1		T54	1		T32	1
all_values[7]	auto[0]	auto[0]	auto[0]	142	1			T54	3		T32	1		T33	2
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T54	1		T32	1		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	138	1			T37	1		T54	3		T33	4
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T37	1		T54	1		T33	2
all_values[7]	auto[1]	auto[0]	auto[1]	180	1			T37	2		T54	2		T32	2
all_values[7]	auto[1]	auto[1]	auto[1]	137	1			T37	3		T54	1		T33	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal