Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::all_modes_cg

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.73	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	1	4	80.00
Crosses	6	2	4	66.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	1	2	66.67	100	1	1	0
cp_tpm_enabled	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	6	2	4	66.67	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	1	2	66.67

Automatically Generated Bins for cp_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[DisabledMode]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[FlashMode]

77369

1

T1

414

T3

380

T4

611

auto[PassthroughMode]

43362

1

T2

24

T9

647

T10

22

---

Summary for Variable cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tpm_enabled

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19984

1

T2

24

T3

380

T4

611

auto[1]

100747

1

T1

414

T6

270

T7

3

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Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	2	4	66.67	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_mode	cp_tpm_enabled	COUNT	AT LEAST	NUMBER	STATUS
[auto[DisabledMode]]	*	--	--	2

Covered bins

cp_mode

cp_tpm_enabled

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[FlashMode]

auto[0]

8458

1

T3

380

T4

611

T22

621

auto[FlashMode]

auto[1]

68911

1

T1

414

T6

270

T7

3

auto[PassthroughMode]

auto[0]

11526

1

T2

24

T10

22

T11

2

auto[PassthroughMode]

auto[1]

31836

1

T9

647

T25

699

T26

541