Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2470524	1			T1	1		T2	17668		T3	1
all_values[1]	2470524	1			T1	1		T2	17668		T3	1
all_values[2]	2470524	1			T1	1		T2	17668		T3	1
all_values[3]	2470524	1			T1	1		T2	17668		T3	1
all_values[4]	2470524	1			T1	1		T2	17668		T3	1
all_values[5]	2470524	1			T1	1		T2	17668		T3	1
all_values[6]	2470524	1			T1	1		T2	17668		T3	1
all_values[7]	2470524	1			T1	1		T2	17668		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19132963

1

T1

8

T2

141299

T3

8

auto[1]

631229

1

T2

45

T67

44

T68

80

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19743370

1

T1

8

T2

141242

T3

8

auto[1]

20822

1

T2

102

T4

4

T14

33

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2397290	1			T1	1		T2	17639		T3	1
all_values[0]	auto[0]	auto[1]	10320	1			T2	22		T14	11		T67	3
all_values[0]	auto[1]	auto[0]	62498	1			T2	4		T67	6		T68	12
all_values[0]	auto[1]	auto[1]	416	1			T2	3		T67	1		T72	1
all_values[1]	auto[0]	auto[0]	2361225	1			T1	1		T2	17643		T3	1
all_values[1]	auto[0]	auto[1]	5094	1			T2	21		T14	11		T67	2
all_values[1]	auto[1]	auto[0]	103928	1			T2	1		T67	2		T68	8
all_values[1]	auto[1]	auto[1]	277	1			T2	3		T68	2		T72	2
all_values[2]	auto[0]	auto[0]	2399478	1			T1	1		T2	17642		T3	1
all_values[2]	auto[0]	auto[1]	2234	1			T2	21		T14	11		T67	2
all_values[2]	auto[1]	auto[0]	68577	1			T2	1		T67	7		T68	4
all_values[2]	auto[1]	auto[1]	235	1			T2	4		T67	2		T68	4
all_values[3]	auto[0]	auto[0]	2407427	1			T1	1		T2	17657		T3	1
all_values[3]	auto[0]	auto[1]	222	1			T2	3		T67	4		T68	2
all_values[3]	auto[1]	auto[0]	62665	1			T2	3		T67	2		T68	10
all_values[3]	auto[1]	auto[1]	210	1			T2	5		T67	2		T68	1
all_values[4]	auto[0]	auto[0]	2371971	1			T1	1		T2	17658		T3	1
all_values[4]	auto[0]	auto[1]	213	1			T2	1		T67	1		T156	6
all_values[4]	auto[1]	auto[0]	98106	1			T2	7		T67	2		T68	9
all_values[4]	auto[1]	auto[1]	234	1			T2	2		T68	1		T72	5
all_values[5]	auto[0]	auto[0]	2384211	1			T1	1		T2	17661		T3	1
all_values[5]	auto[0]	auto[1]	339	1			T2	1		T4	4		T17	1
all_values[5]	auto[1]	auto[0]	85748	1			T67	5		T68	4		T72	6
all_values[5]	auto[1]	auto[1]	226	1			T2	6		T67	4		T68	3
all_values[6]	auto[0]	auto[0]	2405486	1			T1	1		T2	17662		T3	1
all_values[6]	auto[0]	auto[1]	201	1			T2	1		T67	1		T68	2
all_values[6]	auto[1]	auto[0]	64624	1			T67	7		T68	5		T72	4
all_values[6]	auto[1]	auto[1]	213	1			T2	5		T67	1		T68	3
all_values[7]	auto[0]	auto[0]	2387056	1			T1	1		T2	17663		T3	1
all_values[7]	auto[0]	auto[1]	196	1			T2	4		T67	1		T68	1
all_values[7]	auto[1]	auto[0]	83080	1			T2	1		T67	3		T68	10
all_values[7]	auto[1]	auto[1]	192	1			T68	4		T72	4		T35	4