Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	30563	1			T1	2		T2	28		T5	2
auto[SpiFlashAddrCfg]	6458	1			T2	7		T7	10		T9	6
auto[SpiFlashAddr3b]	7925	1			T1	2		T2	14		T7	2
auto[SpiFlashAddr4b]	6518	1			T2	16		T7	4		T9	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28591

1

T1

4

T2

34

T5

2

auto[1]

22873

1

T2

31

T9

24

T12

127

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27404

1

T1

2

T2

38

T6

2

auto[1]

24060

1

T1

2

T2

27

T5

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34547	1			T1	4		T2	35		T5	2
values[1]	851	1			T12	2		T14	6		T28	3
values[2]	1270	1			T2	1		T7	2		T9	4
values[3]	1258	1			T2	2		T10	4		T12	10
values[4]	1248	1			T2	4		T9	2		T10	2
values[5]	1205	1			T2	2		T9	4		T11	2
values[6]	1292	1			T2	3		T7	8		T12	6
values[7]	1235	1			T2	5		T7	4		T12	1
values[8]	8558	1			T2	13		T7	2		T9	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28175

1

T1

4

T5

2

T6

2

auto[1]

23289

1

T2

65

T11

3

T12

409

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

49601

1

T1

4

T2

58

T5

2

write

1863

1

T2

7

T12

6

T14

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16907

1

T2

25

T7

10

T9

14

valids[0x1]

34557

1

T1

4

T2

40

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1292	1			T1	2		T2	2		T5	2
internal_process_ops[0x5a]	1388	1			T1	2		T2	4		T9	2
internal_process_ops[0x05]	18811	1			T2	8		T12	215		T14	224
internal_process_ops[0x35]	1343	1			T2	6		T10	2		T12	12
internal_process_ops[0x15]	1326	1			T6	2		T9	4		T10	2
internal_process_ops[0x03]	863	1			T7	4		T9	2		T12	3
internal_process_ops[0x0b]	947	1			T7	2		T12	4		T14	5
internal_process_ops[0x3b]	931	1			T2	2		T11	2		T12	2
internal_process_ops[0x6b]	964	1			T2	1		T7	2		T9	4
internal_process_ops[0xbb]	956	1			T2	2		T9	2		T10	2
internal_process_ops[0xeb]	923	1			T2	1		T7	8		T14	9

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50559

1

T1

4

T2

64

T5

2

auto[1]

905

1

T2

1

T12

5

T14

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49700

1

T1

4

T2

61

T5

2

auto[1]

1764

1

T2

4

T12

10

T14

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9089

1

T1

2

T5

2

T6

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6589

1

T9

6

T14

99

T29

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1899

1

T7

10

T10

4

T14

24

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1659

1

T9

6

T14

21

T29

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2344

1

T1

2

T7

2

T10

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2060

1

T9

6

T14

23

T28

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1954

1

T7

4

T14

9

T28

15

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1591

1

T9

6

T14

25

T28

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

57

1

T14

2

T22

1

T180

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

61

1

T21

2

T34

3

T35

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

54

1

T28

1

T31

1

T37

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

58

1

T14

1

T28

1

T21

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

81

1

T21

1

T34

1

T181

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

47

1

T14

2

T35

6

T36

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

58

1

T35

2

T36

1

T168

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

76

1

T182

2

T33

4

T34

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

49

1

T14

4

T62

2

T34

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

57

1

T34

1

T35

4

T36

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

68

1

T14

2

T35

4

T22

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

57

1

T14

2

T32

2

T34

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

80

1

T30

2

T31

1

T182

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

62

1

T31

2

T35

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

65

1

T14

2

T31

2

T35

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

60

1

T14

2

T28

2

T21

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8397

1

T2

13

T12

232

T25

22

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6056

1

T2

12

T12

65

T25

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1179

1

T2

4

T11

1

T12

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1225

1

T2

3

T12

14

T25

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1547

1

T2

7

T12

23

T38

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1532

1

T2

6

T12

28

T25

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1285

1

T2

6

T11

2

T12

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1195

1

T2

7

T12

16

T25

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

47

1

T2

2

T95

3

T68

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

54

1

T42

4

T97

1

T89

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

58

1

T2

1

T42

6

T95

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

43

1

T12

1

T42

3

T68

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

57

1

T25

1

T42

2

T87

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

59

1

T12

1

T95

1

T68

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

58

1

T42

2

T96

1

T175

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

60

1

T12

2

T42

3

T148

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

52

1

T42

1

T97

1

T175

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

44

1

T12

1

T42

1

T68

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

62

1

T2

1

T42

1

T68

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

53

1

T42

4

T87

1

T96

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

47

1

T2

2

T42

3

T68

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

43

1

T42

1

T89

2

T81

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

65

1

T12

1

T87

1

T89

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

71

1

T2

1

T95

1

T183

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3688	1			T14	40		T28	36		T21	19
auto[0]	values[0]	valids[0x1]	14533	1			T1	4		T5	2		T6	2
auto[0]	values[1]	valids[0x1]	466	1			T14	6		T28	3		T21	6
auto[0]	values[2]	valids[0x0]	479	1			T7	2		T9	4		T14	8
auto[0]	values[2]	valids[0x1]	289	1			T14	2		T28	5		T21	1
auto[0]	values[3]	valids[0x0]	510	1			T10	4		T14	1		T28	3
auto[0]	values[3]	valids[0x1]	261	1			T14	2		T28	4		T21	2
auto[0]	values[4]	valids[0x0]	475	1			T14	5		T28	4		T43	2
auto[0]	values[4]	valids[0x1]	285	1			T9	2		T10	2		T14	6
auto[0]	values[5]	valids[0x0]	456	1			T9	4		T14	8		T28	12
auto[0]	values[5]	valids[0x1]	226	1			T14	2		T28	2		T184	2
auto[0]	values[6]	valids[0x0]	509	1			T7	8		T14	10		T28	3
auto[0]	values[6]	valids[0x1]	281	1			T14	3		T21	2		T31	3
auto[0]	values[7]	valids[0x0]	498	1			T14	4		T28	4		T21	5
auto[0]	values[7]	valids[0x1]	233	1			T7	4		T14	3		T28	1
auto[0]	values[8]	valids[0x0]	3079	1			T9	6		T10	6		T14	24
auto[0]	values[8]	valids[0x1]	1907	1			T7	2		T14	19		T28	13
auto[1]	values[0]	valids[0x0]	3377	1			T2	9		T12	54		T25	3
auto[1]	values[0]	valids[0x1]	12949	1			T2	26		T12	268		T25	20
auto[1]	values[1]	valids[0x1]	385	1			T12	2		T42	15		T87	2
auto[1]	values[2]	valids[0x0]	288	1			T12	3		T25	1		T42	6
auto[1]	values[2]	valids[0x1]	214	1			T2	1		T12	1		T42	1
auto[1]	values[3]	valids[0x0]	286	1			T12	5		T95	1		T96	3
auto[1]	values[3]	valids[0x1]	201	1			T2	2		T12	5		T42	3
auto[1]	values[4]	valids[0x0]	290	1			T2	4		T12	5		T25	3
auto[1]	values[4]	valids[0x1]	198	1			T12	2		T25	2		T42	6
auto[1]	values[5]	valids[0x0]	307	1			T2	1		T11	2		T12	4
auto[1]	values[5]	valids[0x1]	216	1			T2	1		T12	5		T42	4
auto[1]	values[6]	valids[0x0]	308	1			T12	4		T42	5		T95	10
auto[1]	values[6]	valids[0x1]	194	1			T2	3		T12	2		T42	5
auto[1]	values[7]	valids[0x0]	308	1			T2	4		T12	1		T25	1
auto[1]	values[7]	valids[0x1]	196	1			T2	1		T25	1		T42	5
auto[1]	values[8]	valids[0x0]	2049	1			T2	7		T11	1		T12	16
auto[1]	values[8]	valids[0x1]	1523	1			T2	6		T12	32		T25	3