Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3059090

1

T1

3

T2

3652

T3

484

auto[1]

17433

1

T2

5

T12

209

T14

213

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

869693

1

T1

3

T2

20

T3

484

auto[1]

2206830

1

T2

3637

T12

9787

T14

31318

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	564902	1			T2	1		T3	83		T5	585
auto[524288:1048575]	300017	1			T1	1		T7	70		T11	13494
auto[1048576:1572863]	382705	1			T2	2212		T3	67		T7	2
auto[1572864:2097151]	419306	1			T1	1		T2	1		T3	82
auto[2097152:2621439]	327191	1			T1	1		T7	23		T12	1201
auto[2621440:3145727]	352625	1			T2	653		T3	44		T11	120
auto[3145728:3670015]	354837	1			T2	769		T3	47		T7	282
auto[3670016:4194303]	374940	1			T2	21		T3	161		T5	3

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2228215

1

T1

3

T2

3657

T3

68

auto[1]

848308

1

T3

416

T5

583

T7

215

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2656770

1

T1

3

T2

3135

T3

484

auto[1]

419753

1

T2

522

T12

6704

T14

2396

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	189975	1			T2	1		T3	83		T5	585
auto[0]	auto[0]	auto[0:524287]	auto[1]	329983	1			T12	3		T14	2034		T28	7
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	90333	1			T1	1		T7	70		T11	13494
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	174178	1			T12	256		T14	3280		T28	128
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	98284	1			T2	4		T3	67		T7	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	228096	1			T2	2207		T12	134		T14	2620
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	119041	1			T1	1		T2	1		T3	82
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	240869	1			T12	908		T14	9773		T21	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	72161	1			T1	1		T7	23		T12	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	194215	1			T12	256		T14	2498		T28	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	107820	1			T2	1		T3	44		T11	120
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	186864	1			T2	652		T12	384		T14	3296
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	95929	1			T2	1		T3	47		T7	282
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	215016	1			T2	256		T12	22		T14	3286
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	91557	1			T2	5		T3	161		T5	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	209185	1			T2	3		T12	1028		T14	2048
auto[0]	auto[1]	auto[0:524287]	auto[0]	619	1			T12	5		T42	3		T96	10
auto[0]	auto[1]	auto[0:524287]	auto[1]	41497	1			T12	383		T28	512		T42	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	502	1			T12	1		T14	4		T31	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	33428	1			T14	1		T31	7		T42	257
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	349	1			T14	2		T28	1		T42	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53622	1			T14	261		T31	256		T42	768
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	367	1			T12	7		T42	1		T87	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	56788	1			T12	1846		T42	11		T87	164
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	270	1			T12	3		T14	4		T25	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	58695	1			T12	939		T42	291		T68	1059
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	231	1			T12	2		T21	1		T175	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	55574	1			T12	256		T21	1		T42	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	262	1			T12	2		T14	5		T28	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	41227	1			T2	512		T12	261		T14	1377
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	223	1			T2	3		T12	1		T14	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	71930	1			T2	6		T12	2912		T14	642
auto[1]	auto[0]	auto[0:524287]	auto[0]	226	1			T28	2		T30	2		T25	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1994	1			T28	35		T30	3		T25	15
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	142	1			T14	1		T87	3		T95	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1048	1			T14	18		T87	76		T68	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	191	1			T2	1		T12	3		T42	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1492	1			T12	50		T42	8		T95	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	184	1			T12	1		T87	2		T95	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1460	1			T12	15		T87	9		T95	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	158	1			T31	2		T42	4		T87	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1293	1			T31	16		T42	22		T87	24
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	149	1			T14	1		T21	7		T31	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1523	1			T14	4		T21	120		T31	39
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	178	1			T12	2		T14	3		T28	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1752	1			T12	51		T14	69		T28	49
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	185	1			T2	2		T12	1		T14	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1289	1			T2	1		T14	22		T28	43
auto[1]	auto[1]	auto[0:524287]	auto[0]	45	1			T12	1		T68	1		T101	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	563	1			T12	32		T101	2		T36	63
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	34	1			T14	1		T31	2		T42	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	352	1			T31	39		T34	1		T284	10
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	52	1			T14	2		T95	1		T97	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	619	1			T14	52		T95	4		T89	40
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	49	1			T12	1		T87	1		T35	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	548	1			T12	14		T87	4		T283	126
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	46	1			T42	2		T89	1		T183	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	353	1			T89	23		T183	26		T35	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	42	1			T21	1		T101	3		T34	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	422	1			T21	23		T101	5		T34	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	46	1			T12	1		T42	1		T89	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	427	1			T12	37		T89	2		T36	34
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	43	1			T2	1		T14	2		T31	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	528	1			T14	37		T31	26		T87	11

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1796476	1			T1	3		T2	3131		T3	68
auto[0]	auto[0]	auto[1]	847030	1			T3	416		T5	583		T7	215
auto[0]	auto[1]	auto[0]	414644	1			T2	521		T12	6616		T14	2300
auto[0]	auto[1]	auto[1]	940	1			T12	2		T14	2		T31	1
auto[1]	auto[0]	auto[0]	13002	1			T2	4		T12	123		T14	118
auto[1]	auto[0]	auto[1]	262	1			T14	1		T21	1		T30	1
auto[1]	auto[1]	auto[0]	4093	1			T2	1		T12	86		T14	92
auto[1]	auto[1]	auto[1]	76	1			T14	2		T31	1		T42	1