Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15780

1

T1

4

T5

2

T6

2

auto[1]

12395

1

T9

24

T14

177

T29

6

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3316	1			T7	16		T14	20		T126	6
values[1]	3736	1			T14	169		T29	6		T28	90
values[2]	3624	1			T9	24		T28	20		T195	2
values[3]	3275	1			T10	24		T14	117		T28	57
values[4]	3357	1			T5	2		T6	2		T14	20
values[5]	3777	1			T1	4		T14	25		T21	20
values[6]	3644	1			T14	20		T43	6		T182	20
values[7]	3446	1			T14	62		T28	40		T30	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3526	1			T6	2		T14	20		T28	90
values[1]	3791	1			T14	201		T28	77		T62	27
values[2]	2820	1			T5	2		T21	20		T31	20
values[3]	3514	1			T14	20		T31	146		T32	16
values[4]	3381	1			T28	64		T21	149		T194	12
values[5]	3942	1			T7	16		T9	24		T14	20
values[6]	3544	1			T1	4		T14	75		T126	6
values[7]	3657	1			T10	24		T14	97		T29	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	210	1			T35	52		T170	12		T285	18
auto[0]	values[0]	values[1]	311	1			T62	27		T37	16		T206	9
auto[0]	values[0]	values[2]	209	1			T31	11		T203	14		T36	74
auto[0]	values[0]	values[3]	202	1			T31	6		T208	12		T204	19
auto[0]	values[0]	values[4]	352	1			T37	6		T186	12		T170	25
auto[0]	values[0]	values[5]	287	1			T7	16		T222	22		T206	16
auto[0]	values[0]	values[6]	251	1			T14	9		T126	6		T256	9
auto[0]	values[0]	values[7]	188	1			T35	11		T186	10		T211	14
auto[0]	values[1]	values[0]	289	1			T14	9		T28	78		T180	8
auto[0]	values[1]	values[1]	247	1			T14	18		T60	17		T204	7
auto[0]	values[1]	values[2]	287	1			T21	13		T60	10		T187	77
auto[0]	values[1]	values[3]	256	1			T31	13		T35	8		T80	8
auto[0]	values[1]	values[4]	424	1			T21	116		T194	12		T35	14
auto[0]	values[1]	values[5]	227	1			T36	12		T220	6		T186	12
auto[0]	values[1]	values[6]	227	1			T14	28		T34	9		T168	14
auto[0]	values[1]	values[7]	221	1			T21	56		T34	13		T189	11
auto[0]	values[2]	values[0]	348	1			T37	36		T204	15		T236	13
auto[0]	values[2]	values[1]	251	1			T35	12		T193	44		T229	9
auto[0]	values[2]	values[2]	94	1			T108	16		T22	14		T187	21
auto[0]	values[2]	values[3]	240	1			T35	11		T60	14		T186	11
auto[0]	values[2]	values[4]	309	1			T226	22		T186	22		T208	12
auto[0]	values[2]	values[5]	333	1			T36	74		T196	16		T201	12
auto[0]	values[2]	values[6]	254	1			T195	2		T35	30		T39	6
auto[0]	values[2]	values[7]	228	1			T28	8		T36	10		T60	16
auto[0]	values[3]	values[0]	275	1			T31	15		T215	16		T212	14
auto[0]	values[3]	values[1]	375	1			T28	52		T298	16		T189	11
auto[0]	values[3]	values[2]	170	1			T218	6		T35	11		T229	15
auto[0]	values[3]	values[3]	234	1			T31	15		T174	14		T209	2
auto[0]	values[3]	values[4]	85	1			T189	12		T208	13		T299	13
auto[0]	values[3]	values[5]	220	1			T14	13		T34	11		T60	17
auto[0]	values[3]	values[6]	311	1			T34	9		T36	123		T208	32
auto[0]	values[3]	values[7]	270	1			T10	24		T14	89		T88	14
auto[0]	values[4]	values[0]	219	1			T6	2		T21	9		T35	19
auto[0]	values[4]	values[1]	159	1			T35	7		T300	6		T55	2
auto[0]	values[4]	values[2]	159	1			T5	2		T36	5		T37	9
auto[0]	values[4]	values[3]	323	1			T34	16		T181	87		T186	9
auto[0]	values[4]	values[4]	223	1			T28	12		T21	12		T211	23
auto[0]	values[4]	values[5]	290	1			T213	12		T60	15		T180	11
auto[0]	values[4]	values[6]	166	1			T14	10		T190	14		T198	24
auto[0]	values[4]	values[7]	136	1			T22	12		T206	12		T170	15
auto[0]	values[5]	values[0]	206	1			T184	6		T182	13		T36	22
auto[0]	values[5]	values[1]	253	1			T14	12		T35	11		T180	16
auto[0]	values[5]	values[2]	233	1			T187	10		T170	23		T247	14
auto[0]	values[5]	values[3]	152	1			T37	34		T186	19		T199	8
auto[0]	values[5]	values[4]	338	1			T35	9		T37	94		T170	13
auto[0]	values[5]	values[5]	329	1			T21	10		T88	17		T35	59
auto[0]	values[5]	values[6]	288	1			T1	4		T35	13		T36	10
auto[0]	values[5]	values[7]	386	1			T107	8		T208	12		T191	9
auto[0]	values[6]	values[0]	217	1			T43	6		T182	12		T35	9
auto[0]	values[6]	values[1]	235	1			T227	2		T22	14		T170	48
auto[0]	values[6]	values[2]	166	1			T22	14		T219	18		T216	12
auto[0]	values[6]	values[3]	202	1			T14	13		T34	14		T35	13
auto[0]	values[6]	values[4]	257	1			T35	70		T82	20		T180	14
auto[0]	values[6]	values[5]	297	1			T168	74		T206	14		T214	11
auto[0]	values[6]	values[6]	308	1			T35	6		T37	10		T210	2
auto[0]	values[6]	values[7]	259	1			T34	16		T36	67		T217	6
auto[0]	values[7]	values[0]	263	1			T30	23		T172	6		T168	9
auto[0]	values[7]	values[1]	229	1			T14	55		T28	12		T224	2
auto[0]	values[7]	values[2]	155	1			T189	11		T170	11		T214	9
auto[0]	values[7]	values[3]	222	1			T109	8		T207	14		T180	29
auto[0]	values[7]	values[4]	125	1			T189	11		T191	14		T249	14
auto[0]	values[7]	values[5]	250	1			T31	59		T170	13		T204	12
auto[0]	values[7]	values[6]	238	1			T34	12		T168	7		T180	52
auto[0]	values[7]	values[7]	312	1			T28	15		T185	8		T34	10
auto[1]	values[0]	values[0]	117	1			T35	22		T170	15		T259	16
auto[1]	values[0]	values[1]	213	1			T37	4		T206	11		T189	9
auto[1]	values[0]	values[2]	136	1			T31	9		T36	10		T22	10
auto[1]	values[0]	values[3]	174	1			T31	57		T32	16		T208	8
auto[1]	values[0]	values[4]	185	1			T37	37		T186	8		T170	73
auto[1]	values[0]	values[5]	105	1			T206	8		T208	19		T228	7
auto[1]	values[0]	values[6]	157	1			T14	11		T256	32		T23	13
auto[1]	values[0]	values[7]	219	1			T35	9		T186	17		T211	6
auto[1]	values[1]	values[0]	122	1			T14	11		T28	12		T180	12
auto[1]	values[1]	values[1]	278	1			T14	96		T60	23		T204	17
auto[1]	values[1]	values[2]	130	1			T21	7		T60	42		T187	30
auto[1]	values[1]	values[3]	304	1			T31	48		T35	12		T36	9
auto[1]	values[1]	values[4]	210	1			T21	13		T35	6		T22	14
auto[1]	values[1]	values[5]	254	1			T36	8		T186	8		T208	67
auto[1]	values[1]	values[6]	153	1			T14	7		T34	11		T168	6
auto[1]	values[1]	values[7]	107	1			T29	6		T21	6		T34	7
auto[1]	values[2]	values[0]	197	1			T37	9		T204	8		T236	7
auto[1]	values[2]	values[1]	166	1			T35	17		T229	11		T247	9
auto[1]	values[2]	values[2]	225	1			T22	7		T187	53		T301	111
auto[1]	values[2]	values[3]	179	1			T35	9		T60	7		T186	17
auto[1]	values[2]	values[4]	202	1			T186	19		T302	2		T208	10
auto[1]	values[2]	values[5]	251	1			T9	24		T36	12		T201	32
auto[1]	values[2]	values[6]	166	1			T35	15		T168	6		T204	13
auto[1]	values[2]	values[7]	181	1			T28	12		T36	10		T60	10
auto[1]	values[3]	values[0]	159	1			T31	32		T200	8		T189	12
auto[1]	values[3]	values[1]	114	1			T28	5		T189	12		T205	4
auto[1]	values[3]	values[2]	86	1			T35	9		T229	5		T247	5
auto[1]	values[3]	values[3]	224	1			T31	7		T180	12		T170	11
auto[1]	values[3]	values[4]	62	1			T189	8		T208	14		T299	7
auto[1]	values[3]	values[5]	310	1			T14	7		T34	9		T60	9
auto[1]	values[3]	values[6]	186	1			T34	12		T36	59		T208	8
auto[1]	values[3]	values[7]	194	1			T14	8		T88	6		T182	10
auto[1]	values[4]	values[0]	192	1			T21	11		T35	21		T37	38
auto[1]	values[4]	values[1]	176	1			T35	13		T168	5		T211	8
auto[1]	values[4]	values[2]	208	1			T33	24		T36	56		T37	11
auto[1]	values[4]	values[3]	304	1			T34	4		T186	13		T189	6
auto[1]	values[4]	values[4]	208	1			T28	52		T21	8		T211	42
auto[1]	values[4]	values[5]	330	1			T60	6		T180	39		T206	4
auto[1]	values[4]	values[6]	110	1			T14	10		T187	12		T171	12
auto[1]	values[4]	values[7]	154	1			T22	9		T206	8		T170	5
auto[1]	values[5]	values[0]	313	1			T182	7		T36	136		T37	16
auto[1]	values[5]	values[1]	202	1			T14	13		T35	9		T180	5
auto[1]	values[5]	values[2]	232	1			T187	10		T170	42		T247	6
auto[1]	values[5]	values[3]	167	1			T37	15		T186	3		T199	53
auto[1]	values[5]	values[4]	155	1			T35	11		T37	7		T170	12
auto[1]	values[5]	values[5]	151	1			T21	10		T88	3		T35	18
auto[1]	values[5]	values[6]	167	1			T35	10		T36	10		T22	7
auto[1]	values[5]	values[7]	205	1			T208	8		T191	17		T252	23
auto[1]	values[6]	values[0]	180	1			T182	8		T35	15		T22	6
auto[1]	values[6]	values[1]	290	1			T22	10		T170	111		T214	9
auto[1]	values[6]	values[2]	144	1			T22	9		T216	8		T170	15
auto[1]	values[6]	values[3]	231	1			T14	7		T34	6		T35	9
auto[1]	values[6]	values[4]	170	1			T35	5		T180	24		T187	7
auto[1]	values[6]	values[5]	207	1			T168	8		T206	6		T214	20
auto[1]	values[6]	values[6]	204	1			T35	36		T37	19		T189	11
auto[1]	values[6]	values[7]	277	1			T192	16		T34	11		T36	17
auto[1]	values[7]	values[0]	219	1			T168	11		T171	10		T292	61
auto[1]	values[7]	values[1]	292	1			T14	7		T28	8		T34	3
auto[1]	values[7]	values[2]	186	1			T197	6		T189	16		T170	9
auto[1]	values[7]	values[3]	100	1			T180	11		T186	4		T206	8
auto[1]	values[7]	values[4]	76	1			T189	9		T191	6		T249	9
auto[1]	values[7]	values[5]	101	1			T31	4		T170	10		T204	8
auto[1]	values[7]	values[6]	358	1			T34	10		T168	26		T180	5
auto[1]	values[7]	values[7]	320	1			T28	5		T34	10		T35	45