Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	403	1			T14	9		T28	6		T194	4
auto[ReadAddrCrossIntoMailbox]	305	1			T7	2		T14	2		T28	1
auto[ReadAddrCrossOutOfMailbox]	282	1			T14	4		T21	2		T31	1
auto[ReadAddrCrossAllMailbox]	170	1			T14	3		T28	1		T21	1
auto[ReadAddrOutsideMailbox]	3103	1			T7	14		T9	8		T10	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2129

1

T7

8

T9

4

T10

3

auto[1]

2134

1

T7

8

T9

4

T10

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	667	1			T7	4		T9	2		T14	6
read_ops[0x0b]	714	1			T7	2		T14	5		T28	4
read_ops[0x3b]	711	1			T14	7		T28	3		T43	2
read_ops[0x6b]	739	1			T7	2		T9	4		T10	4
read_ops[0xbb]	691	1			T9	2		T10	2		T14	4
read_ops[0xeb]	741	1			T7	8		T14	9		T28	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T14	2		T28	2		T182	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T35	2		T80	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T7	1		T21	1		T35	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T7	1		T60	1		T168	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T21	1		T35	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T35	2		T60	1		T180	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T185	1		T35	2		T80	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T185	1		T35	3		T80	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T7	1		T9	1		T14	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	203	1			T7	1		T9	1		T28	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T226	1		T35	3		T168	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T226	1		T35	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T14	1		T226	1		T37	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T14	1		T31	2		T226	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T226	1		T35	2		T200	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T14	1		T226	1		T35	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T35	1		T236	1		T303	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T168	2		T186	2		T187	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T7	1		T28	2		T30	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T7	1		T14	2		T28	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T14	2		T28	1		T194	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T14	2		T194	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T35	2		T36	1		T196	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T35	1		T196	1		T168	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T35	1		T196	1		T206	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T34	1		T35	2		T196	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T14	1		T37	2		T206	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T31	1		T35	1		T37	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T14	2		T43	1		T21	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	242	1			T28	2		T43	1		T21	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T14	1		T35	1		T36	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T28	1		T168	1		T208	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T28	1		T35	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T35	2		T196	1		T187	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T14	1		T196	2		T229	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T34	2		T35	1		T196	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T14	1		T21	1		T35	3
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T263	1		T304	1		T152	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T7	1		T9	2		T10	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T7	1		T9	2		T10	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T28	1		T35	5		T37	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T35	2		T36	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T31	2		T37	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T35	1		T36	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T14	1		T36	2		T37	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T21	1		T36	1		T60	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T14	1		T35	1		T211	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T35	1		T170	1		T305	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	242	1			T9	1		T10	1		T21	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	258	1			T9	1		T10	1		T14	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T194	1		T174	4		T35	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	53	1			T14	2		T28	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T186	1		T206	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T35	3		T37	1		T168	3
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T109	3		T206	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T14	1		T31	1		T35	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T37	2		T186	1		T269	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T28	1		T204	1		T249	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T7	4		T21	1		T30	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	274	1			T7	4		T14	6		T28	4