Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2470524	1			T1	1		T2	17668		T3	1
all_pins[1]	2470524	1			T1	1		T2	17668		T3	1
all_pins[2]	2470524	1			T1	1		T2	17668		T3	1
all_pins[3]	2470524	1			T1	1		T2	17668		T3	1
all_pins[4]	2470524	1			T1	1		T2	17668		T3	1
all_pins[5]	2470524	1			T1	1		T2	17668		T3	1
all_pins[6]	2470524	1			T1	1		T2	17668		T3	1
all_pins[7]	2470524	1			T1	1		T2	17668		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19696537	1			T1	8		T2	141316		T3	8
values[0x1]	67655	1			T2	28		T67	10		T68	18
transitions[0x0=>0x1]	66943	1			T2	18		T67	9		T68	14
transitions[0x1=>0x0]	66952	1			T2	18		T67	9		T68	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2470089	1			T1	1		T2	17665		T3	1
all_pins[0]	values[0x1]	435	1			T2	3		T67	1		T72	1
all_pins[0]	transitions[0x0=>0x1]	375	1			T2	2		T67	1		T72	1
all_pins[0]	transitions[0x1=>0x0]	230	1			T2	2		T68	2		T72	2
all_pins[1]	values[0x0]	2470234	1			T1	1		T2	17665		T3	1
all_pins[1]	values[0x1]	290	1			T2	3		T68	2		T72	2
all_pins[1]	transitions[0x0=>0x1]	228	1			T2	1		T35	71		T179	1
all_pins[1]	transitions[0x1=>0x0]	176	1			T2	2		T67	2		T68	2
all_pins[2]	values[0x0]	2470286	1			T1	1		T2	17664		T3	1
all_pins[2]	values[0x1]	238	1			T2	4		T67	2		T68	4
all_pins[2]	transitions[0x0=>0x1]	182	1			T2	2		T67	1		T68	3
all_pins[2]	transitions[0x1=>0x0]	154	1			T2	3		T67	1		T72	2
all_pins[3]	values[0x0]	2470314	1			T1	1		T2	17663		T3	1
all_pins[3]	values[0x1]	210	1			T2	5		T67	2		T68	1
all_pins[3]	transitions[0x0=>0x1]	160	1			T2	5		T67	2		T68	1
all_pins[3]	transitions[0x1=>0x0]	184	1			T2	2		T68	1		T72	2
all_pins[4]	values[0x0]	2470290	1			T1	1		T2	17666		T3	1
all_pins[4]	values[0x1]	234	1			T2	2		T68	1		T72	5
all_pins[4]	transitions[0x0=>0x1]	175	1			T2	1		T68	1		T72	4
all_pins[4]	transitions[0x1=>0x0]	1577	1			T2	5		T67	4		T68	3
all_pins[5]	values[0x0]	2468888	1			T1	1		T2	17662		T3	1
all_pins[5]	values[0x1]	1636	1			T2	6		T67	4		T68	3
all_pins[5]	transitions[0x0=>0x1]	1304	1			T2	2		T67	4		T68	2
all_pins[5]	transitions[0x1=>0x0]	64088	1			T2	1		T67	1		T68	2
all_pins[6]	values[0x0]	2406104	1			T1	1		T2	17663		T3	1
all_pins[6]	values[0x1]	64420	1			T2	5		T67	1		T68	3
all_pins[6]	transitions[0x0=>0x1]	64377	1			T2	5		T67	1		T68	3
all_pins[6]	transitions[0x1=>0x0]	149	1			T68	4		T72	3		T35	1
all_pins[7]	values[0x0]	2470332	1			T1	1		T2	17668		T3	1
all_pins[7]	values[0x1]	192	1			T68	4		T72	4		T35	4
all_pins[7]	transitions[0x0=>0x1]	142	1			T68	4		T72	3		T35	2
all_pins[7]	transitions[0x1=>0x0]	394	1			T2	3		T67	1		T72	1