Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3178	1			T14	40		T29	6		T28	20
values[1]	3899	1			T28	40		T21	60		T88	20
values[2]	3952	1			T1	4		T14	158		T43	6
values[3]	3779	1			T5	2		T9	24		T14	62
values[4]	3582	1			T6	2		T21	20		T31	83
values[5]	3496	1			T14	20		T28	70		T21	129
values[6]	2957	1			T14	35		T28	64		T31	63
values[7]	3332	1			T7	16		T10	24		T14	118

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3376	1			T14	20		T28	20		T43	6
values[1]	3882	1			T14	138		T28	40		T185	8
values[2]	3622	1			T14	87		T28	64		T88	20
values[3]	3671	1			T7	16		T14	55		T29	6
values[4]	3690	1			T28	20		T30	23		T31	20
values[5]	3453	1			T1	4		T10	24		T14	20
values[6]	3438	1			T5	2		T6	2		T9	24
values[7]	3043	1			T21	20		T31	61		T88	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27697

1

T1

4

T5

2

T6

2

auto[1]

478

1

T14

7

T28

3

T21

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2]]	[values[0]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	404	1			T14	20		T28	19		T186	22
auto[0]	values[0]	values[1]	405	1			T109	8		T187	27		T188	18
auto[0]	values[0]	values[2]	554	1			T37	20		T168	20		T187	20
auto[0]	values[0]	values[3]	448	1			T29	6		T33	20		T35	49
auto[0]	values[0]	values[4]	443	1			T34	19		T107	8		T60	48
auto[0]	values[0]	values[5]	340	1			T60	25		T189	27		T170	24
auto[0]	values[0]	values[6]	294	1			T14	20		T184	6		T189	20
auto[0]	values[0]	values[7]	222	1			T172	6		T180	20		T186	40
auto[0]	values[1]	values[0]	756	1			T35	28		T36	103		T190	14
auto[0]	values[1]	values[1]	540	1			T28	38		T32	12		T189	19
auto[0]	values[1]	values[2]	266	1			T88	20		T37	20		T55	2
auto[0]	values[1]	values[3]	440	1			T62	27		T170	18		T191	20
auto[0]	values[1]	values[4]	491	1			T192	16		T34	21		T193	44
auto[0]	values[1]	values[5]	634	1			T21	20		T35	36		T36	85
auto[0]	values[1]	values[6]	375	1			T21	18		T182	18		T60	20
auto[0]	values[1]	values[7]	330	1			T21	20		T194	12		T35	40
auto[0]	values[2]	values[0]	590	1			T43	6		T34	21		T58	4
auto[0]	values[2]	values[1]	637	1			T14	135		T31	22		T22	20
auto[0]	values[2]	values[2]	474	1			T195	2		T35	92		T196	16
auto[0]	values[2]	values[3]	352	1			T14	18		T22	23		T60	21
auto[0]	values[2]	values[4]	518	1			T35	40		T197	6		T180	21
auto[0]	values[2]	values[5]	337	1			T1	4		T34	20		T198	24
auto[0]	values[2]	values[6]	480	1			T36	52		T170	60		T199	136
auto[0]	values[2]	values[7]	501	1			T22	46		T60	24		T200	20
auto[0]	values[3]	values[0]	326	1			T21	62		T201	41		T202	20
auto[0]	values[3]	values[1]	509	1			T185	8		T31	47		T174	14
auto[0]	values[3]	values[2]	342	1			T14	62		T182	20		T35	52
auto[0]	values[3]	values[3]	688	1			T181	87		T186	23		T189	29
auto[0]	values[3]	values[4]	455	1			T28	20		T34	35		T36	62
auto[0]	values[3]	values[5]	609	1			T28	57		T203	14		T36	20
auto[0]	values[3]	values[6]	455	1			T5	2		T9	24		T204	19
auto[0]	values[3]	values[7]	319	1			T189	23		T187	20		T170	50
auto[0]	values[4]	values[0]	400	1			T21	19		T186	22		T205	4
auto[0]	values[4]	values[1]	435	1			T31	63		T22	21		T206	20
auto[0]	values[4]	values[2]	401	1			T35	38		T82	20		T180	38
auto[0]	values[4]	values[3]	415	1			T34	20		T37	19		T207	14
auto[0]	values[4]	values[4]	541	1			T31	20		T39	6		T36	91
auto[0]	values[4]	values[5]	415	1			T36	19		T170	26		T208	27
auto[0]	values[4]	values[6]	542	1			T6	2		T37	91		T209	2
auto[0]	values[4]	values[7]	367	1			T88	20		T210	2		T211	20
auto[0]	values[5]	values[0]	245	1			T35	20		T206	42		T187	41
auto[0]	values[5]	values[1]	390	1			T34	19		T212	14		T168	20
auto[0]	values[5]	values[2]	639	1			T35	20		T213	12		T36	17
auto[0]	values[5]	values[3]	459	1			T37	28		T60	20		T214	18
auto[0]	values[5]	values[4]	389	1			T30	23		T80	8		T170	20
auto[0]	values[5]	values[5]	369	1			T14	19		T28	70		T215	16
auto[0]	values[5]	values[6]	392	1			T21	125		T126	6		T206	42
auto[0]	values[5]	values[7]	555	1			T37	43		T216	20		T208	52
auto[0]	values[6]	values[0]	280	1			T31	61		T35	87		T37	48
auto[0]	values[6]	values[1]	411	1			T34	27		T36	138		T22	15
auto[0]	values[6]	values[2]	527	1			T28	64		T35	44		T180	47
auto[0]	values[6]	values[3]	333	1			T14	35		T182	20		T217	6
auto[0]	values[6]	values[4]	422	1			T218	6		T37	20		T219	18
auto[0]	values[6]	values[5]	321	1			T220	6		T221	8		T206	34
auto[0]	values[6]	values[6]	370	1			T22	22		T180	23		T191	56
auto[0]	values[6]	values[7]	258	1			T222	22		T223	2		T180	55
auto[0]	values[7]	values[0]	315	1			T224	2		T35	97		T186	28
auto[0]	values[7]	values[1]	489	1			T22	20		T60	21		T211	20
auto[0]	values[7]	values[2]	356	1			T14	24		T187	22		T225	4
auto[0]	values[7]	values[3]	475	1			T7	16		T226	22		T35	20
auto[0]	values[7]	values[4]	364	1			T227	2		T22	20		T168	79
auto[0]	values[7]	values[5]	364	1			T10	24		T37	99		T228	29
auto[0]	values[7]	values[6]	484	1			T14	93		T189	22		T229	22
auto[0]	values[7]	values[7]	440	1			T31	60		T35	19		T36	139
auto[1]	values[0]	values[0]	12	1			T28	1		T230	1		T231	8
auto[1]	values[0]	values[1]	9	1			T187	1		T232	2		T233	2
auto[1]	values[0]	values[2]	6	1			T170	1		T230	1		T234	2
auto[1]	values[0]	values[3]	14	1			T33	4		T35	2		T235	2
auto[1]	values[0]	values[4]	12	1			T34	1		T60	4		T216	2
auto[1]	values[0]	values[5]	8	1			T60	1		T170	1		T236	1
auto[1]	values[0]	values[6]	1	1			T237	1		-	-		-	-
auto[1]	values[0]	values[7]	6	1			T170	2		T204	3		T238	1
auto[1]	values[1]	values[0]	10	1			T35	1		T36	3		T22	1
auto[1]	values[1]	values[1]	11	1			T28	2		T32	4		T189	1
auto[1]	values[1]	values[2]	9	1			T168	1		T200	1		T171	3
auto[1]	values[1]	values[3]	8	1			T170	2		T239	2		T240	4
auto[1]	values[1]	values[4]	8	1			T208	2		T228	1		T48	3
auto[1]	values[1]	values[5]	6	1			T35	2		T36	1		T241	1
auto[1]	values[1]	values[6]	13	1			T21	2		T182	2		T242	4
auto[1]	values[1]	values[7]	2	1			T23	1		T238	1		-	-
auto[1]	values[2]	values[1]	8	1			T14	3		T243	1		T233	1
auto[1]	values[2]	values[2]	17	1			T35	6		T204	1		T244	2
auto[1]	values[2]	values[3]	5	1			T14	2		T22	1		T23	1
auto[1]	values[2]	values[4]	9	1			T189	1		T170	1		T237	3
auto[1]	values[2]	values[5]	8	1			T23	1		T245	2		T246	1
auto[1]	values[2]	values[6]	8	1			T36	1		T170	1		T199	2
auto[1]	values[2]	values[7]	8	1			T22	1		T60	2		T247	1
auto[1]	values[3]	values[0]	14	1			T201	3		T22	1		T60	2
auto[1]	values[3]	values[1]	8	1			T34	1		T35	2		T248	2
auto[1]	values[3]	values[2]	2	1			T35	2		-	-		-	-
auto[1]	values[3]	values[3]	14	1			T189	1		T211	1		T249	3
auto[1]	values[3]	values[4]	9	1			T34	5		T233	1		T250	1
auto[1]	values[3]	values[5]	17	1			T186	1		T189	2		T208	1
auto[1]	values[3]	values[6]	6	1			T204	1		T232	2		T251	2
auto[1]	values[3]	values[7]	6	1			T252	2		T253	4		-	-
auto[1]	values[4]	values[0]	10	1			T21	1		T247	4		T249	2
auto[1]	values[4]	values[1]	4	1			T191	1		T254	1		T255	2
auto[1]	values[4]	values[2]	12	1			T35	2		T180	2		T150	3
auto[1]	values[4]	values[3]	6	1			T37	1		T170	4		T252	1
auto[1]	values[4]	values[4]	7	1			T36	1		T247	1		T256	2
auto[1]	values[4]	values[5]	13	1			T36	1		T204	4		T247	1
auto[1]	values[4]	values[6]	5	1			T37	1		T257	1		T258	3
auto[1]	values[4]	values[7]	9	1			T204	1		T259	2		T260	2
auto[1]	values[5]	values[0]	5	1			T206	1		T187	1		T216	1
auto[1]	values[5]	values[1]	10	1			T34	1		T180	1		T261	3
auto[1]	values[5]	values[2]	6	1			T36	3		T191	1		T23	1
auto[1]	values[5]	values[3]	5	1			T37	1		T214	2		T53	2
auto[1]	values[5]	values[4]	11	1			T256	1		T262	5		T246	4
auto[1]	values[5]	values[5]	7	1			T14	1		T252	2		T230	1
auto[1]	values[5]	values[6]	4	1			T21	4		-	-		-	-
auto[1]	values[5]	values[7]	10	1			T252	2		T244	2		T263	1
auto[1]	values[6]	values[0]	5	1			T31	2		T37	2		T253	1
auto[1]	values[6]	values[1]	13	1			T22	6		T186	1		T23	2
auto[1]	values[6]	values[2]	4	1			T208	1		T171	1		T255	2
auto[1]	values[6]	values[3]	2	1			T237	1		T251	1		-	-
auto[1]	values[6]	values[4]	3	1			T264	2		T265	1		-	-
auto[1]	values[6]	values[5]	1	1			T189	1		-	-		-	-
auto[1]	values[6]	values[6]	2	1			T22	2		-	-		-	-
auto[1]	values[6]	values[7]	5	1			T180	2		T244	1		T266	2
auto[1]	values[7]	values[0]	4	1			T245	3		T240	1		-	-
auto[1]	values[7]	values[1]	3	1			T252	1		T267	2		-	-
auto[1]	values[7]	values[2]	7	1			T14	1		T257	1		T268	3
auto[1]	values[7]	values[3]	7	1			T200	2		T211	2		T269	1
auto[1]	values[7]	values[4]	8	1			T168	3		T230	2		T270	1
auto[1]	values[7]	values[5]	4	1			T37	2		T241	1		T253	1
auto[1]	values[7]	values[6]	7	1			T229	1		T247	2		T252	2
auto[1]	values[7]	values[7]	5	1			T31	1		T35	1		T36	1