Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1727

1

T2

2

T14

4

T15

7

auto[1]

1774

1

T2

10

T14

7

T15

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1955

1

T2

12

T14

11

T15

11

auto[1]

1546

1

T16

13

T18

7

T94

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2760

1

T2

8

T14

7

T15

8

auto[1]

741

1

T2

4

T14

4

T15

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	687	1			T2	1		T14	1		T15	2
valid[1]	684	1			T2	3		T14	2		T15	1
valid[2]	694	1			T2	3		T14	1		T15	3
valid[3]	709	1			T2	2		T14	3		T15	3
valid[4]	727	1			T2	3		T14	4		T15	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	104	1			T15	1		T95	1		T96	2
auto[0]	auto[0]	valid[0]	auto[1]	155	1			T16	2		T104	3		T98	3
auto[0]	auto[0]	valid[1]	auto[0]	144	1			T2	1		T15	1		T95	1
auto[0]	auto[0]	valid[1]	auto[1]	145	1			T104	1		T98	1		T96	2
auto[0]	auto[0]	valid[2]	auto[0]	104	1			T15	1		T88	1		T42	1
auto[0]	auto[0]	valid[2]	auto[1]	151	1			T16	2		T18	4		T104	2
auto[0]	auto[0]	valid[3]	auto[0]	108	1			T88	1		T42	1		T99	3
auto[0]	auto[0]	valid[3]	auto[1]	149	1			T16	1		T18	1		T104	1
auto[0]	auto[0]	valid[4]	auto[0]	137	1			T14	1		T15	2		T67	1
auto[0]	auto[0]	valid[4]	auto[1]	158	1			T16	5		T94	4		T98	7
auto[0]	auto[1]	valid[0]	auto[0]	120	1			T2	1		T14	1		T15	1
auto[0]	auto[1]	valid[0]	auto[1]	175	1			T16	1		T18	1		T94	2
auto[0]	auto[1]	valid[1]	auto[0]	108	1			T2	2		T14	1		T42	2
auto[0]	auto[1]	valid[1]	auto[1]	159	1			T94	2		T104	1		T98	5
auto[0]	auto[1]	valid[2]	auto[0]	127	1			T2	2		T15	2		T88	2
auto[0]	auto[1]	valid[2]	auto[1]	136	1			T18	1		T94	1		T98	3
auto[0]	auto[1]	valid[3]	auto[0]	137	1			T2	1		T14	3		T87	2
auto[0]	auto[1]	valid[3]	auto[1]	166	1			T16	2		T104	2		T98	5
auto[0]	auto[1]	valid[4]	auto[0]	125	1			T2	1		T14	1		T88	1
auto[0]	auto[1]	valid[4]	auto[1]	152	1			T104	1		T98	3		T100	2
auto[1]	auto[0]	valid[0]	auto[0]	67	1			T97	1		T175	1		T178	1
auto[1]	auto[0]	valid[1]	auto[0]	58	1			T14	1		T88	1		T96	1
auto[1]	auto[0]	valid[2]	auto[0]	93	1			T14	1		T42	1		T97	2
auto[1]	auto[0]	valid[3]	auto[0]	79	1			T15	2		T99	1		T96	1
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T2	1		T14	1		T88	2
auto[1]	auto[1]	valid[0]	auto[0]	66	1			T88	1		T99	1		T95	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T88	1		T99	1		T96	1
auto[1]	auto[1]	valid[2]	auto[0]	83	1			T2	1		T68	2		T97	1
auto[1]	auto[1]	valid[3]	auto[0]	70	1			T2	1		T15	1		T95	1
auto[1]	auto[1]	valid[4]	auto[0]	80	1			T2	1		T14	1		T88	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal