Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48772

1

T2

293

T4

6

T14

205

auto[1]

15380

1

T16

13

T18

7

T94

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46715

1

T2

208

T4

2

T14

137

auto[1]

17437

1

T2

85

T4

4

T14

68

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33092	1			T2	145		T4	3		T14	95
others[1]	5383	1			T2	26		T4	1		T14	20
others[2]	5435	1			T2	24		T14	17		T15	20
others[3]	6206	1			T2	31		T14	22		T15	36
interest[1]	3515	1			T2	22		T4	1		T14	9
interest[4]	21690	1			T2	87		T4	2		T14	60
interest[64]	10521	1			T2	45		T4	1		T14	42

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16089	1			T2	109		T4	1		T14	65
auto[0]	auto[0]	others[1]	2627	1			T2	18		T4	1		T14	14
auto[0]	auto[0]	others[2]	2669	1			T2	13		T14	12		T15	13
auto[0]	auto[0]	others[3]	3044	1			T2	21		T14	13		T15	26
auto[0]	auto[0]	interest[1]	1687	1			T2	15		T14	6		T15	8
auto[0]	auto[0]	interest[4]	10506	1			T2	61		T4	1		T14	41
auto[0]	auto[0]	interest[64]	5219	1			T2	32		T14	27		T15	32
auto[0]	auto[1]	others[0]	8106	1			T16	13		T18	7		T94	9
auto[0]	auto[1]	others[1]	1263	1			T87	1		T98	32		T95	2
auto[0]	auto[1]	others[2]	1297	1			T87	1		T98	42		T95	6
auto[0]	auto[1]	others[3]	1452	1			T87	1		T98	40		T95	3
auto[0]	auto[1]	interest[1]	788	1			T98	20		T95	4		T96	7
auto[0]	auto[1]	interest[4]	5423	1			T16	13		T18	7		T94	9
auto[0]	auto[1]	interest[64]	2474	1			T87	1		T98	70		T95	4
auto[1]	auto[0]	others[0]	8897	1			T2	36		T4	2		T14	30
auto[1]	auto[0]	others[1]	1493	1			T2	8		T14	6		T15	5
auto[1]	auto[0]	others[2]	1469	1			T2	11		T14	5		T15	7
auto[1]	auto[0]	others[3]	1710	1			T2	10		T14	9		T15	10
auto[1]	auto[0]	interest[1]	1040	1			T2	7		T4	1		T14	3
auto[1]	auto[0]	interest[4]	5761	1			T2	26		T4	1		T14	19
auto[1]	auto[0]	interest[64]	2828	1			T2	13		T4	1		T14	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal