Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	928	1			T2	10		T67	10		T68	11
all_values[1]	928	1			T2	10		T67	10		T68	11
all_values[2]	928	1			T2	10		T67	10		T68	11
all_values[3]	928	1			T2	10		T67	10		T68	11
all_values[4]	928	1			T2	10		T67	10		T68	11
all_values[5]	928	1			T2	10		T67	10		T68	11
all_values[6]	928	1			T2	10		T67	10		T68	11
all_values[7]	928	1			T2	10		T67	10		T68	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3906

1

T2

37

T67

41

T68

42

auto[1]

3518

1

T2

43

T67

39

T68

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3010

1

T2

24

T67

39

T68

41

auto[1]

4414

1

T2

56

T67

41

T68

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4237

1

T2

35

T67

46

T68

53

auto[1]

3187

1

T2

45

T67

34

T68

35

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	208	1			T67	2		T68	1		T72	8
all_values[0]	auto[0]	auto[0]	auto[1]	100	1			T2	1		T67	1		T68	2
all_values[0]	auto[0]	auto[1]	auto[0]	142	1			T2	3		T67	1		T68	6
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T2	1		T35	1		T46	3
all_values[0]	auto[1]	auto[0]	auto[1]	226	1			T2	1		T67	2		T68	1
all_values[0]	auto[1]	auto[1]	auto[1]	177	1			T2	4		T67	4		T68	1
all_values[1]	auto[0]	auto[0]	auto[0]	183	1			T2	2		T67	5		T68	4
all_values[1]	auto[0]	auto[0]	auto[1]	93	1			T67	1		T72	2		T35	1
all_values[1]	auto[0]	auto[1]	auto[0]	170	1			T2	1		T67	2		T68	3
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T2	1		T68	1		T72	1
all_values[1]	auto[1]	auto[0]	auto[1]	213	1			T2	3		T67	2		T68	2
all_values[1]	auto[1]	auto[1]	auto[1]	179	1			T2	3		T68	1		T72	1
all_values[2]	auto[0]	auto[0]	auto[0]	189	1			T2	2		T68	4		T72	3
all_values[2]	auto[0]	auto[0]	auto[1]	92	1			T2	2		T68	1		T72	2
all_values[2]	auto[0]	auto[1]	auto[0]	149	1			T67	3		T72	1		T35	2
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T2	2		T67	1		T68	2
all_values[2]	auto[1]	auto[0]	auto[1]	196	1			T2	1		T67	2		T68	1
all_values[2]	auto[1]	auto[1]	auto[1]	208	1			T2	3		T67	4		T68	3
all_values[3]	auto[0]	auto[0]	auto[0]	189	1			T2	1		T68	1		T72	3
all_values[3]	auto[0]	auto[0]	auto[1]	93	1			T67	1		T68	1		T72	4
all_values[3]	auto[0]	auto[1]	auto[0]	169	1			T2	1		T67	2		T68	5
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T2	2		T67	1		T68	1
all_values[3]	auto[1]	auto[0]	auto[1]	226	1			T2	3		T67	4		T68	2
all_values[3]	auto[1]	auto[1]	auto[1]	169	1			T2	3		T67	2		T68	1
all_values[4]	auto[0]	auto[0]	auto[0]	171	1			T2	1		T67	6		T68	4
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T72	4		T179	3		T46	1
all_values[4]	auto[0]	auto[1]	auto[0]	165	1			T2	3		T67	1		T68	2
all_values[4]	auto[0]	auto[1]	auto[1]	100	1			T72	2		T35	2		T179	1
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T2	3		T67	2		T68	2
all_values[4]	auto[1]	auto[1]	auto[1]	219	1			T2	3		T67	1		T68	3
all_values[5]	auto[0]	auto[0]	auto[0]	270	1			T2	3		T68	1		T72	7
all_values[5]	auto[0]	auto[1]	auto[0]	252	1			T67	4		T68	2		T72	4
all_values[5]	auto[1]	auto[0]	auto[1]	189	1			T67	2		T68	7		T72	3
all_values[5]	auto[1]	auto[1]	auto[1]	217	1			T2	7		T67	4		T68	1
all_values[6]	auto[0]	auto[0]	auto[0]	202	1			T2	2		T67	2		T68	3
all_values[6]	auto[0]	auto[0]	auto[1]	99	1			T67	1		T68	1		T72	3
all_values[6]	auto[0]	auto[1]	auto[0]	163	1			T67	4		T72	2		T35	1
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T2	2		T68	1		T72	1
all_values[6]	auto[1]	auto[0]	auto[1]	202	1			T2	3		T67	1		T68	3
all_values[6]	auto[1]	auto[1]	auto[1]	178	1			T2	3		T67	2		T68	3
all_values[7]	auto[0]	auto[0]	auto[0]	202	1			T2	4		T67	4		T72	3
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T67	1		T68	1		T179	1
all_values[7]	auto[0]	auto[1]	auto[0]	186	1			T2	1		T67	3		T68	5
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T68	1		T72	1		T35	1
all_values[7]	auto[1]	auto[0]	auto[1]	214	1			T2	5		T67	2		T72	4
all_values[7]	auto[1]	auto[1]	auto[1]	181	1			T68	4		T72	5		T35	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal