Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2428443	1			T1	126		T2	2		T3	15
all_values[1]	2428443	1			T1	126		T2	2		T3	15
all_values[2]	2428443	1			T1	126		T2	2		T3	15
all_values[3]	2428443	1			T1	126		T2	2		T3	15
all_values[4]	2428443	1			T1	126		T2	2		T3	15
all_values[5]	2428443	1			T1	126		T2	2		T3	15
all_values[6]	2428443	1			T1	126		T2	2		T3	15
all_values[7]	2428443	1			T1	126		T2	2		T3	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19286097

1

T1

1008

T2

16

T3

120

auto[1]

141447

1

T6

27062

T10

20

T26

12600

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19406194

1

T1

1008

T2

16

T3

120

auto[1]

21350

1

T6

238

T7

2

T10

116

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2402628	1			T1	126		T2	2		T3	15
all_values[0]	auto[0]	auto[1]	11122	1			T6	1		T10	73		T18	3
all_values[0]	auto[1]	auto[0]	14231	1			T6	8898		T10	1		T26	5
all_values[0]	auto[1]	auto[1]	462	1			T6	121		T10	3		T26	6
all_values[1]	auto[0]	auto[0]	2420678	1			T1	126		T2	2		T3	15
all_values[1]	auto[0]	auto[1]	5268	1			T6	79		T10	15		T20	12
all_values[1]	auto[1]	auto[0]	2307	1			T6	1		T10	1		T26	4
all_values[1]	auto[1]	auto[1]	190	1			T10	1		T26	8		T34	3
all_values[2]	auto[0]	auto[0]	2407287	1			T1	126		T2	2		T3	15
all_values[2]	auto[0]	auto[1]	1964	1			T6	26		T10	15		T26	60
all_values[2]	auto[1]	auto[0]	18898	1			T26	5		T62	3		T34	7
all_values[2]	auto[1]	auto[1]	294	1			T10	2		T26	1		T62	1
all_values[3]	auto[0]	auto[0]	2403198	1			T1	126		T2	2		T3	15
all_values[3]	auto[0]	auto[1]	206	1			T26	2		T62	2		T34	2
all_values[3]	auto[1]	auto[0]	24862	1			T6	9018		T10	4		T26	10
all_values[3]	auto[1]	auto[1]	177	1			T6	2		T10	1		T26	4
all_values[4]	auto[0]	auto[0]	2410986	1			T1	126		T2	2		T3	15
all_values[4]	auto[0]	auto[1]	211	1			T6	3		T26	4		T62	2
all_values[4]	auto[1]	auto[0]	17047	1			T6	1		T26	2		T34	5
all_values[4]	auto[1]	auto[1]	199	1			T10	1		T26	11		T62	1
all_values[5]	auto[0]	auto[0]	2397216	1			T1	126		T2	2		T3	15
all_values[5]	auto[0]	auto[1]	328	1			T6	1		T7	2		T10	2
all_values[5]	auto[1]	auto[0]	30722	1			T6	1		T10	1		T26	4178
all_values[5]	auto[1]	auto[1]	177	1			T26	4		T34	2		T149	5
all_values[6]	auto[0]	auto[0]	2423603	1			T1	126		T2	2		T3	15
all_values[6]	auto[0]	auto[1]	200	1			T6	3		T26	3		T62	3
all_values[6]	auto[1]	auto[0]	4467	1			T10	1		T26	4179		T34	9
all_values[6]	auto[1]	auto[1]	173	1			T26	6		T62	1		T34	1
all_values[7]	auto[0]	auto[0]	2401011	1			T1	126		T2	2		T3	15
all_values[7]	auto[0]	auto[1]	191	1			T10	1		T26	7		T62	1
all_values[7]	auto[1]	auto[0]	27053	1			T6	9018		T10	2		T26	4170
all_values[7]	auto[1]	auto[1]	188	1			T6	2		T10	2		T26	7