Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	27586	1			T1	2		T6	447		T8	2
auto[SpiFlashAddrCfg]	6024	1			T1	4		T6	70		T8	6
auto[SpiFlashAddr3b]	7314	1			T1	2		T6	77		T8	6
auto[SpiFlashAddr4b]	6068	1			T1	2		T6	53		T8	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27688

1

T1

10

T6

337

T8

16

auto[1]

19304

1

T6

310

T10

375

T18

19

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25485

1

T1

8

T6

185

T8

6

auto[1]

21507

1

T1

2

T6

462

T8

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	31078	1			T1	2		T6	478		T8	4
values[1]	851	1			T1	4		T6	3		T9	2
values[2]	1156	1			T6	14		T10	8		T18	4
values[3]	1160	1			T6	19		T10	9		T18	1
values[4]	1174	1			T1	2		T6	10		T10	12
values[5]	1210	1			T6	19		T8	6		T9	2
values[6]	1242	1			T6	14		T10	11		T13	2
values[7]	1193	1			T1	2		T6	14		T10	8
values[8]	7928	1			T6	76		T8	6		T10	97

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28480

1

T1

10

T6

647

T8

16

auto[1]

18512

1

T10

752

T20

327

T23

192

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

45410

1

T1

10

T6

629

T8

16

write

1582

1

T6

18

T10

9

T18

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15915

1

T1

2

T6

156

T8

10

valids[0x1]

31077

1

T1

8

T6

491

T8

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1252	1			T6	11		T10	11		T64	6
internal_process_ops[0x5a]	1171	1			T6	12		T9	2		T10	14
internal_process_ops[0x05]	16619	1			T6	336		T8	2		T10	421
internal_process_ops[0x35]	1174	1			T6	20		T10	13		T82	2
internal_process_ops[0x15]	1276	1			T6	9		T10	16		T13	4
internal_process_ops[0x03]	896	1			T6	9		T10	3		T18	2
internal_process_ops[0x0b]	923	1			T6	8		T10	5		T18	3
internal_process_ops[0x3b]	906	1			T6	11		T8	2		T9	2
internal_process_ops[0x6b]	942	1			T6	9		T8	4		T10	2
internal_process_ops[0xbb]	933	1			T6	16		T10	2		T13	2
internal_process_ops[0xeb]	913	1			T6	8		T8	2		T10	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46217

1

T1

10

T6

635

T8

16

auto[1]

775

1

T6

12

T10

5

T20

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45378

1

T1

10

T6

628

T8

16

auto[1]

1614

1

T6

19

T10

24

T18

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10153

1

T1

2

T6

235

T8

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5692

1

T6

206

T18

9

T28

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2011

1

T1

4

T6

33

T8

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1716

1

T6

35

T18

1

T28

28

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2413

1

T1

2

T6

39

T8

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1962

1

T6

36

T18

4

T28

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1918

1

T1

2

T6

20

T8

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1682

1

T6

25

T18

5

T28

15

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

72

1

T6

1

T28

2

T29

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

54

1

T6

1

T30

1

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

61

1

T6

1

T29

3

T31

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

45

1

T6

3

T32

4

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

64

1

T6

1

T29

2

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

60

1

T29

1

T151

2

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

55

1

T6

1

T28

1

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

64

1

T30

1

T31

1

T34

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

72

1

T18

1

T28

1

T151

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

32

1

T34

1

T36

2

T37

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

47

1

T29

1

T46

4

T152

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

73

1

T6

2

T28

1

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

73

1

T6

2

T30

1

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

63

1

T6

5

T29

2

T151

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

49

1

T31

1

T151

4

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

49

1

T6

1

T29

1

T30

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

6979

1

T10

269

T20

127

T23

80

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4401

1

T10

279

T20

40

T23

18

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

944

1

T10

32

T20

31

T23

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

926

1

T10

16

T20

20

T23

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1392

1

T10

41

T20

28

T23

20

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1163

1

T10

43

T20

19

T23

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1043

1

T10

31

T20

24

T23

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1015

1

T10

32

T20

31

T23

17

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

43

1

T10

2

T20

1

T23

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

25

1

T43

1

T44

3

T45

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

21

1

T26

2

T45

1

T112

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

40

1

T20

1

T26

3

T43

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

37

1

T26

2

T52

1

T153

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

54

1

T10

2

T20

2

T26

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

52

1

T10

1

T26

2

T43

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

41

1

T10

3

T20

2

T23

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

47

1

T23

4

T26

1

T154

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

52

1

T23

3

T26

1

T44

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

24

1

T20

1

T23

1

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

37

1

T26

3

T62

1

T52

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

51

1

T26

4

T44

3

T155

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

36

1

T26

1

T43

1

T52

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

39

1

T10

1

T23

4

T112

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

50

1

T26

3

T52

1

T54

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3801	1			T6	54		T9	4		T12	16
auto[0]	values[0]	valids[0x1]	14494	1			T1	2		T6	424		T8	4
auto[0]	values[1]	valids[0x1]	499	1			T1	4		T6	3		T9	2
auto[0]	values[2]	valids[0x0]	484	1			T6	12		T18	2		T28	11
auto[0]	values[2]	valids[0x1]	274	1			T6	2		T18	2		T28	3
auto[0]	values[3]	valids[0x0]	506	1			T6	12		T28	9		T29	8
auto[0]	values[3]	valids[0x1]	243	1			T6	7		T18	1		T28	7
auto[0]	values[4]	valids[0x0]	497	1			T1	2		T6	7		T28	6
auto[0]	values[4]	valids[0x1]	263	1			T6	3		T28	3		T29	5
auto[0]	values[5]	valids[0x0]	506	1			T6	12		T8	4		T9	2
auto[0]	values[5]	valids[0x1]	283	1			T6	7		T8	2		T18	1
auto[0]	values[6]	valids[0x0]	488	1			T6	8		T13	2		T28	6
auto[0]	values[6]	valids[0x1]	275	1			T6	6		T18	2		T28	3
auto[0]	values[7]	valids[0x0]	503	1			T6	12		T18	1		T28	1
auto[0]	values[7]	valids[0x1]	273	1			T1	2		T6	2		T28	1
auto[0]	values[8]	valids[0x0]	3161	1			T6	39		T8	6		T13	2
auto[0]	values[8]	valids[0x1]	1930	1			T6	37		T18	2		T28	12
auto[1]	values[0]	valids[0x0]	2756	1			T10	72		T20	51		T23	40
auto[1]	values[0]	valids[0x1]	10027	1			T10	511		T20	129		T23	80
auto[1]	values[1]	valids[0x1]	352	1			T10	15		T20	5		T23	5
auto[1]	values[2]	valids[0x0]	241	1			T10	4		T20	10		T23	5
auto[1]	values[2]	valids[0x1]	157	1			T10	4		T20	3		T26	2
auto[1]	values[3]	valids[0x0]	240	1			T10	3		T20	6		T23	5
auto[1]	values[3]	valids[0x1]	171	1			T10	6		T20	1		T23	4
auto[1]	values[4]	valids[0x0]	266	1			T10	10		T20	9		T23	1
auto[1]	values[4]	valids[0x1]	148	1			T10	2		T20	2		T23	2
auto[1]	values[5]	valids[0x0]	236	1			T10	4		T20	8		T23	3
auto[1]	values[5]	valids[0x1]	185	1			T10	5		T20	3		T26	5
auto[1]	values[6]	valids[0x0]	303	1			T10	6		T20	11		T23	7
auto[1]	values[6]	valids[0x1]	176	1			T10	5		T20	2		T23	5
auto[1]	values[7]	valids[0x0]	265	1			T10	6		T20	8		T23	3
auto[1]	values[7]	valids[0x1]	152	1			T10	2		T20	3		T23	1
auto[1]	values[8]	valids[0x0]	1662	1			T10	51		T20	47		T23	17
auto[1]	values[8]	valids[0x1]	1175	1			T10	46		T20	29		T23	14