Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2755699

1

T1

1

T2

1

T5

1

auto[1]

15310

1

T6

327

T10

412

T18

2

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

839892

1

T1

1

T2

1

T5

1

auto[1]

1931117

1

T6

24234

T10

11544

T13

8

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	443065	1			T1	1		T2	1		T5	1
auto[524288:1048575]	288611	1			T6	2659		T10	2714		T12	1243
auto[1048576:1572863]	349304	1			T6	8289		T10	2774		T13	260
auto[1572864:2097151]	312186	1			T6	135		T10	4		T12	1
auto[2097152:2621439]	324953	1			T6	4770		T10	1183		T12	2
auto[2621440:3145727]	353941	1			T6	157		T10	1197		T12	973
auto[3145728:3670015]	298879	1			T6	795		T10	99		T12	639
auto[3670016:4194303]	400070	1			T6	3225		T10	2869		T12	611

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1948478

1

T1

1

T2

1

T5

1

auto[1]

822531

1

T6

8

T10

9

T12

3449

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2450071

1

T1

1

T2

1

T5

1

auto[1]

320938

1

T6

3671

T10

2302

T14

177

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	135455	1			T1	1		T2	1		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	263147	1			T6	3998		T10	769		T13	3
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	91824	1			T6	6		T10	2		T12	1243
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	162911	1			T6	2653		T10	2628		T20	1173
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	110907	1			T6	12		T10	12		T13	258
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	193069	1			T6	7363		T10	941		T13	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	91980	1			T6	7		T12	1		T13	128
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	175040	1			T6	128		T10	4		T20	7047
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	82791	1			T6	14		T10	13		T12	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	206932	1			T6	2885		T10	796		T13	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	134605	1			T6	8		T10	9		T12	973
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	176202	1			T6	132		T10	1031		T20	6102
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	66508	1			T6	5		T10	3		T12	639
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	189024	1			T6	6		T10	2		T18	516
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	112333	1			T6	7		T10	8		T12	611
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	244619	1			T6	3145		T10	2853		T64	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	446	1			T6	2		T10	4		T20	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	41679	1			T6	257		T10	3		T26	2284
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2773	1			T23	1		T26	2		T43	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	29211	1			T23	1		T26	1		T43	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3140	1			T6	3		T10	10		T20	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	39798	1			T6	772		T10	1724		T26	257
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1295	1			T23	1		T133	5		T26	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	42239	1			T23	47		T26	771		T28	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1390	1			T6	4		T10	5		T14	177
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	32064	1			T6	1818		T10	261		T20	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1365	1			T6	1		T20	7		T26	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	40586	1			T10	143		T20	1		T26	129
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	580	1			T6	2		T10	3		T23	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	40313	1			T6	769		T10	1		T23	2148
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	880	1			T28	3		T29	4		T31	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40593	1			T26	512		T28	516		T29	259
auto[1]	auto[0]	auto[0:524287]	auto[0]	216	1			T6	2		T10	1		T18	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1856	1			T6	35		T10	10		T18	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	163	1			T10	2		T20	2		T26	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1361	1			T10	82		T20	34		T26	30
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	176	1			T6	5		T10	1		T23	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1887	1			T6	119		T10	40		T26	58
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	153	1			T20	2		T43	1		T28	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1039	1			T20	17		T43	31		T28	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	165	1			T6	2		T10	3		T20	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1180	1			T6	23		T10	69		T20	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	119	1			T6	4		T10	3		T20	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	864	1			T6	12		T10	11		T20	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	171	1			T6	1		T10	2		T26	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1923	1			T6	8		T10	32		T26	177
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	159	1			T6	2		T10	1		T26	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1292	1			T6	71		T10	7		T26	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	41	1			T10	3		T28	1		T29	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	225	1			T10	7		T28	7		T29	8
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	49	1			T23	1		T26	1		T43	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	319	1			T23	3		T26	38		T43	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	44	1			T6	1		T10	5		T26	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	283	1			T6	14		T10	41		T26	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	41	1			T23	1		T26	3		T29	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	399	1			T23	7		T26	7		T29	54
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	43	1			T6	1		T10	2		T23	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	388	1			T6	23		T10	34		T23	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	33	1			T20	1		T26	1		T151	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	167	1			T26	1		T151	5		T54	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	25	1			T6	1		T10	1		T44	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	335	1			T6	3		T10	55		T44	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	22	1			T35	1		T154	1		T155	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	172	1			T35	4		T154	8		T155	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1624611	1			T1	1		T2	1		T5	1
auto[0]	auto[0]	auto[1]	812736	1			T6	4		T10	3		T12	3449
auto[0]	auto[1]	auto[0]	308835	1			T6	3626		T10	2149		T14	1
auto[0]	auto[1]	auto[1]	9517	1			T6	2		T10	5		T14	176
auto[1]	auto[0]	auto[0]	12495	1			T6	282		T10	264		T18	2
auto[1]	auto[0]	auto[1]	229	1			T6	2		T43	4		T28	1
auto[1]	auto[1]	auto[0]	2537	1			T6	43		T10	147		T20	1
auto[1]	auto[1]	auto[1]	49	1			T10	1		T26	1		T44	1